EP0459753A2
Expired / Lapsed
EP
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Network access controller having logical FIFO buffer
Assignee: Advanced Micro Devices Inc
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Filing: 1991-05-28
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Granted: —
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Expires: 2011-05-28
Abstract
Abstract A network interface interconnects a processor and a memory residing on a system bus having a predetermined average bus latency to a network containing other processors and memories. The interface, which is implemented using a bus master architecture, includes a network access controller for accessing data on the network, a random access memory, preferably in the form of an SRAM as a buffer between the network and system bus, and a network DMA controller. The Network Access Controller configures the buffer to have at least one logical FIFO for storing data; the size of the logical FIFO is related to the predetermined average bus latency. The DMA controller further controls transfer of data between the system memory and the network through the logical FIFOs. Preferably, the buffer is configured to have (1) a first logical FIFO for storing incoming data from the network and (2) at least one additional logical FIFO for storing outgoing data from said system memory to the network. Frames of data in the buffer are demarked by tag and status bits. The interface has particular utility in an FDDI type local area network.
Inventors
- 👤 Farzin Firoozmand
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 21:05
CPC Classifications
H; H04; H04L; H04L47/00; H04L47/50; H04L47/62; H04L47/6215; H04L49/00; H04L49/90; H04L49/9036; H04L49/9063; H04L49/9068; H04L49/9073
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
122 words
In a network comprising a processor and a system memory residing on a system bus, a bus master architecture for interfacing the system bus to a network containing other processors and system memories, wherein the system bus has a predetermined average system bus latency, a network interface, comprising: a network access controller means for accessing data on said network; a random access memory; said network access controller means including means for configuring said random access memory to have at least one logical FIFO for storing data, the size of said logical FIFO being related to said predetermined average system bus latency; and network DMA controller means for controlling transfer of data between said system memory and said at least one logical FIFO.
Claim 2
Dependent Claim
20 words
The interface of claim 1, wherein said random access memory means is comprised of a static random access memory (SRAM).
Claim 3
Dependent Claim
27 words
The interface of claim 2, wherein said static random access memory comprises an SRAM external to said network access controller means and said network DMA controller means.
Claim 4
Dependent Claim
34 words
The interface of claim 2, wherein said static random access memory comprises an SRAM on a common chip with at least one of said network access controller means and said network DMA controller means.
Claim 5
Dependent Claim
35 words
The interface of claim 1, wherein at least one of said network controller means and said network DMA controller means includes an on-chip FIFO to compensate for mismatches between system bus and network clock rates.
Claim 6
Dependent Claim
64 words
The interface of claim 1, wherein said network access controller means includes means for configuring said random access memory to have (1) a first logical FIFO for storing data incoming from said network access controller means to said memory controller means and (2) at least one additional logical FIFO for storing data outgoing from said DMA controller means to said network access controller means.
Claim 7
Dependent Claim
49 words
The interface of claim 6, wherein said DMA controller means includes means for formatting data packets stored in said system memory into frames to be transmitted on said network bus and for storing said frames in said first logical FIFO sequentially and contiguously to form at least one queue.
Claim 8
Dependent Claim
43 words
The interface of claim 7, wherein said network access controller means includes means responsive to a request for transmission for reading a number of said frames in sequence from said first logical FIFO and for transmitting said number of frames on said network.
Claim 9
Dependent Claim
41 words
The interface of claim 7, wherein said network access controller means includes means for receiving frames of data on said network and for storing said frames sequentially in said at least one additional logical FIFO to form at least one queue.
Claim 10
Dependent Claim
40 words
The interface of claim 9, wherein said DMA controller means includes means for reading said at least one queue of data frames in said at least one additional logical FIFO and for transmitting said data frames to said system memory.
Claim 11
Dependent Claim
14 words
The interface of claim 7, wherein boundaries between frames are demarked by tag bits.
Claim 12
Dependent Claim
13 words
The interface of claim 7, wherein status bits are appended to each frame.
Claim 13
Dependent Claim
100 words
In a network comprising a processor and a system memory residing on a system bus, a method for interfacing said system bus to a network containing other processors and system memories, wherein the system bus has a predetermined average system bus latency, comprising the steps of: accessing data on said network; configuring a random access memory to have at least one logical FIFO for storing data, the size of said logical FIFO being related to said predetermined average system bus latency; and controlling transfer of data between said system memory and said network through said at least one logical FIFO.
Claim 14
Dependent Claim
52 words
The method of claim 13, wherein said step of configuring includes the steps of configuring said random access memory to have (1) a first logical FIFO for storing incoming data from said network and (2) at least one additional logical FIFO for storing outgoing data from said system memory to said network.
Claim 15
Dependent Claim
120 words
For a Fiber Distributed Digital Interface (FDDI) network having a plurality of processors each having a system memory and residing on a system bus having a predetermined average system bus latency, and an optical medium forming a digital data communication path among said processors, a network controller, comprising: first means implementing a timed token data protocol for accessing said optical medium; a random access memory means; second means for configuring said random access memory means to have at least one logical FIFO for storing packet data, the size of said logical FIFO being related to said predetermined average system bus latency; and third means for controlling transfer of data between said system memory and said at least one logical FIFO.
Claim 16
Dependent Claim
21 words
The network controller of claim 15, wherein said random access memory means is comprised of a static random access memory (SRAM).
Claim 17
Dependent Claim
23 words
The network controller of claim 16, wherein said static random access memory comprises an SRAM external to said first, second and third means.
Claim 18
Dependent Claim
36 words
The network controller of claim 16, wherein said static random access memory means comprises an SRAM on a common chip with at least one of (a) said first and second means and (b) said third means.
Claim 19
Dependent Claim
37 words
The controller of claim 15, wherein at least one of (1) said first and second means and (2) said third means includes an on-chip FIFO to compensate for mismatches between system bus and optical medium clock rates.
Claim 20
Dependent Claim
58 words
The controller of claim 15, wherein said second means includes means for configuring said random access memory to have (1) a first logical FIFO for storing data incoming from said third means to said first means and (2) at least one additional logical FIFO for storing data outgoing from said first and second means to said third means.
Claim 21
Dependent Claim
48 words
The controller of claim 20, wherein said second means includes means for formatting data packets stored in said system memory into frames to be transmitted on said optical medium and for storing said frames in said first logical FIFO sequentially and contiguously to form at least one queue.
Claim 22
Dependent Claim
42 words
The controller of claim 21, wherein said first means includes means responsive to a request for transmission for reading a number of said frames in sequence from said first logical FIFO and for transmitting said number of frames on said optical medium.
Claim 23
Dependent Claim
42 words
The controller of claim 21, wherein said first and second means includes means for receiving frames of data on said optical medium and includes means for storing said frames sequentially in said at least one additional logical FIFO to form a queue.
Claim 24
Dependent Claim
36 words
The controller of claim 21, wherein said third means includes means for reading said queue of data frames in said at least one additional logical FIFO and for transmitting said data frames to said system memory.
Claim 25
Dependent Claim
14 words
The controller of claim 21, wherein boundaries between frames are demarked by tag bits.
Claim 26
Dependent Claim
13 words
The controller of claim 21, wherein status bits are appended to each frame.
Claim 27
Dependent Claim
125 words
For a Fiber Distributed Digital Interface (FDDI) network having a plurality of processors each having a system memory and residing on a system bus having a predetermined average system bus latency, and an optical medium forming a digital data communication path carrying data packets among said processors and memories, a method of interfacing said system bus and said optical medium, comprising the steps of: accessing said optical medium in response to predetermined conditions; configuring a random access memory means to have at least one logical FIFO for storing packet data, the size of said logical FIFO being related to said predetermined average system bus latency; and controlling transfer of data between said system memory and said optical medium through said at least one logical FIFO.
Claim 28
Dependent Claim
54 words
The method of claim 27, wherein said step of configuring includes the steps of configuring said random access memory to have (1) a first logical FIFO for storing incoming data from said optical medium and (2) at least one additional logical FIFO for storing outgoing data from said system memory to said optical medium.
References Cited (Backward Citations)
No citation records indexed.
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