DMA controller with mechanism for conditional action under control of status register, prespecified parameters, and condition field of channel command

Claim 1

A direct memory access (DMA) controller comprising a channel including: a status register; a first condition register; a command buffer having a first condition field; a first combinational logic block having inputs connected to said status register, said first condition register and said first condition field and having an output whose value determines the conditional execution of a first action by said controller; and wherein said first combinational logic block includes a first subsystem having inputs connected to said status register and said first condition register and having an output, and a second subsystem having inputs connected to said first condition field and said output of said first subsystem, and an output which is the output of said first combinational logic; said first condition field has two bits and four possible values, said values being used to determine whether said output of said second subsystem is one, zero, equal to said output of said first subsystem, or equal to the complement of the output of said first subsystem; and said first condition register has a mask field and a value field and the output of said first subsystem is one if and only if those bits of said status register corresponding to one bits of said mask field are equal to the corresponding bits of said value field.