US6049476A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High memory capacity DIMM with data and state memory
Assignee: Morgan Stanley and Co LLC
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Filing: 1998-07-31
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Granted: 2000-04-11
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Expires: 2018-07-31
Abstract
Abstract A high memory capacity dual in-line memory module (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system including a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM can be configured in a plurality of storage capacities.
Inventors
- 👤 James P. Laudon
- 👤 Daniel E. Lenoski
- 👤 John Manton
- 👤 Michael E. Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:52
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/02; G11C5/04; G06; G06F; G06F12/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
105 words
A dual in-line memory module (DIMM) comprising: a circuit board; and a plurality of semiconductor memory chips mounted on said circuit board, said memory chips being logically organized into a first memory bank portion and a second memory bank portion, wherein said first and second memory bank portions are separately addressable, wherein said first memory bank portion is logically organized into memory blocks for storing data, and wherein said second memory bank portion is configured to store directory information for said memory blocks of said first memory bank portion, and wherein said plurality of semiconductor memory chips provide 128M of data storage on the DIMM.
Claim 2
Dependent Claim
105 words
A dual in-line memory module (DIMM) comprising: a circuit board; and a plurality of semiconductor memory chips mounted on said circuit board, said memory chips being logically organized into a first memory bank portion and a second memory bank portion, wherein said first and second memory bank portions are separately addressable, wherein said first memory bank portion is logically organized into memory blocks for storing data, and wherein said second memory bank portion is configured to store directory information for said memory blocks of said first memory bank portion, and wherein said plurality of semiconductor memory chips provide 128M of data storage on the DIMM.
Claim 3
Dependent Claim
40 words
The DIMM of claim 1, wherein said memory chips are selected from the group consisting of sixteen megabit by four bit (16M×4), eight megabit by eight bit (8M×8), four megabit by 16 bit (4M×16) SDRAM chips and any combination thereof.
Claim 4
Dependent Claim
110 words
A pair of dual in-line memory modules (DIMMs), each DIMM comprising: a circuit board; and a plurality of semiconductor memory chips mounted on said circuit board, said memory chips being logically organized into a first memory bank portion and a second memory bank portion, wherein said first and second memory bank portions are separately addressable, wherein said first memory bank portion is logically organized into memory blocks for storing data, and wherein said second memory bank portion is configured to store directory information for said memory blocks of said first memory bank portion, and wherein said plurality of semiconductor memory chips provide 256M of data storage on the DIMM pair.
Claim 5
Dependent Claim
110 words
A pair of dual in-line memory modules (DIMMs), each DIMM comprising: a circuit board; and a plurality of semiconductor memory chips mounted on said circuit board, said memory chips being logically organized into a first memory bank portion and a second memory bank portion, wherein said first and second memory bank portions are separately addressable, wherein said first memory bank portion is logically organized into memory blocks for storing data, and wherein said second memory bank portion is configured to store directory information for said memory blocks of said first memory bank portion, and wherein said plurality of semiconductor memory chips provide 256M of data storage on the DIMM pair.
Claim 6
Dependent Claim
40 words
The DIMM of claim 3, wherein said memory chips are selected from the group consisting of sixteen megabit by four bit (16M×4), eight megabit by eight bit (8M×8), four megabit by 16 bit (4M×16) SDRAM chips and any combination thereof.
Claim 7
Dependent Claim
117 words
A piggyback dual in-line memory module (DIMM) comprising: a circuit board having a piggyback board mounted thereon; and a plurality of semiconductor memory chips mounted on said circuit board and said piggyback board, said memory chips being logically organized into a first memory bank portion and a second memory bank portion, wherein said first and second memory bank portions are separately addressable, wherein said first memory bank portion is logically organized into memory blocks for storing data, and wherein said second memory bank portion is configured to store directory information for said memory blocks of said first memory bank portion, and wherein said plurality of semiconductor memory chips provide 256M of data storage on the piggyback DIMM.
Claim 8
Dependent Claim
117 words
A piggyback dual in-line memory module (DIMM) comprising: a circuit board having a piggyback board mounted thereon; and a plurality of semiconductor memory chips mounted on said circuit board and said piggyback board, said memory chips being logically organized into a first memory bank portion and a second memory bank portion, wherein said first and second memory bank portions are separately addressable, wherein said first memory bank portion is logically organized into memory blocks for storing data, and wherein said second memory bank portion is configured to store directory information for said memory blocks of said first memory bank portion, and wherein said plurality of semiconductor memory chips provide 256M of data storage on the piggyback DIMM.
Claim 9
Dependent Claim
40 words
The DIMM of claim 5, wherein said memory chips are selected from the group consisting of sixteen megabit by four bit (16M×4), eight megabit by eight bit (8M×8), four megabit by 16 bit (4M×16) SDRAM chips and any combination thereof.
Claim 10
Dependent Claim
122 words
A pair of piggyback dual in-line memory modules (DIMMs), each DIMM comprising: a circuit board having a piggyback board mounted thereon; and a plurality of semiconductor memory chips mounted on said circuit board and said piggyback board, said memory chips being logically organized into a first memory bank portion and a second memory bank portion, wherein said first and second memory bank portions are separately addressable, wherein said first memory bank portion is logically organized into memory blocks for storing data, and wherein said second memory bank portion is configured to store directory information for said memory blocks of said first memory bank portion, and wherein said plurality of semiconductor memory chips provide 512M of data storage on the piggyback DIMM pair.
Claim 11
Dependent Claim
122 words
A pair of piggyback dual in-line memory modules (DIMMs), each DIMM comprising: a circuit board having a piggyback board mounted thereon; and a plurality of semiconductor memory chips mounted on said circuit board and said piggyback board, said memory chips being logically organized into a first memory bank portion and a second memory bank portion, wherein said first and second memory bank portions are separately addressable, wherein said first memory bank portion is logically organized into memory blocks for storing data, and wherein said second memory bank portion is configured to store directory information for said memory blocks of said first memory bank portion, and wherein said plurality of semiconductor memory chips provide 512M of data storage on the piggyback DIMM pair.
Claim 12
Dependent Claim
40 words
The DIMM of claim 7, wherein said memory chips are selected from the group consisting of thirty-two megabit by four bit (32M×4), sixteen megabit by eight bit (16M×8), eight megabit by sixteen bit (8M×16) SDRAM chips and any combination thereof.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-04-11 | 2003-10-11 | 2004-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-04-11 | 2007-10-11 | 2008-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-04-11 | 2011-10-11 | 2012-04-11 | $7700.00 | Window Closed / Lapsed |