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US6048740A
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Ferroelectric nonvolatile transistor and method of making same
Assignee: Sharp Laboratories of America Inc
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Filing: 1998-11-05
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Granted: 2000-04-11
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Expires: 2018-11-05
Abstract
Abstract A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of δ, includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2≧L1+2δ; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure. A ferroelectric memory transistor includes a silicon substrate having a p- well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure having an opening having a width of L1 located about said gate region; a FE gate stack formed in said FE gate stack surround structure, wherein said FE gate stack has a width of L2, wherein L2≧L1+2δ, wherein δ is the alignment tolerance of the lithographic process.
Inventors
- 👤 Sheng Teng Hsu
- 👤 Jer-shen Maa
- 👤 Fengyang Zhang
- 👤 Tingkai Li
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:08
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/01; H10D30/021; H10D30/0415; H10D30/701
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
263 words
A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of δ, comprising: preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a ferroelectric (FE) gate stack surround structure for surrounding a ferroelectric (FE) gate stack which is formed in a subsequent step, the step of forming a FE gate stack surround structure including depositing a PSG layer by CVD at a temperature of between about 300° C. and 500° C. having a thickness of between about 100 nm to 300 nm over the device area; and depositing an oxide layer over the PSG layer to a thickness of between about 20 nm to 50 nm; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing, by CVD, oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2≧L1+2δ; depositing a first insulating layer over the structure; implanting arsenic ions to form a source region and a drain region; and annealing the structure, including forming a lightly doped source region and a lightly doped drain region in the silicon substrate below the PSG by heating the structure at a temperature of between 600° C. to 1,000° C. for between about 10 minutes and 60 minutes.
Claim 2
Independent Claim
263 words
A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of δ, comprising: preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a ferroelectric (FE) gate stack surround structure for surrounding a ferroelectric (FE) gate stack which is formed in a subsequent step, the step of forming a FE gate stack surround structure including depositing a PSG layer by CVD at a temperature of between about 300° C. and 500° C. having a thickness of between about 100 nm to 300 nm over the device area; and depositing an oxide layer over the PSG layer to a thickness of between about 20 nm to 50 nm; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing, by CVD, oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2≧L1+2δ; depositing a first insulating layer over the structure; implanting arsenic ions to form a source region and a drain region; and annealing the structure, including forming a lightly doped source region and a lightly doped drain region in the silicon substrate below the PSG by heating the structure at a temperature of between 600° C. to 1,000° C. for between about 10 minutes and 60 minutes.
Claim 3
Dependent Claim
61 words
The method of claim 1 wherein said step of forming a FE gate stack includes depositing a bottom electrode to a thickness of between about 10 nm to 40 nm, depositing the ferroelectric material to a thickness of between about 100 nm to 400 nm, and depositing the top electrode to a thickness of between about 10 nm to 40 nm.
Claim 4
Dependent Claim
27 words
The method of claim 2 wherein said depositing the bottom and top electrode includes depositing material taken from the group consisting of Pt, Ir and Pt/Ir alloy.
Claim 5
Dependent Claim
49 words
The method of claim 2 wherein said depositing the ferroelectric material includes depositing a FE layer of material taken from the group consisting of Pb(Zr, Ti)O 3 (PZT), PLZT, SrBi 2 Ta 2 O 9 (SBT), Pb 5 Ge 3 O 11 , BaTiO 3 and LiNbO 3 .
Claim 6
Independent Claim
244 words
A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of δ, comprising: preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a ferroelectric (FE) gate stack surround structure for surrounding a ferroelectric (FE) gate stack which is formed in a subsequent step, the step of forming a FE gate stack surround structure including depositing a layer of phosphorous silicate glass (PSG) on the substrate; and depositing an oxide layer over the PSG layer; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing, by CVD, oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2≧L1+2δ; depositing a first insulating layer over the structure; implanting arsenic ions to form a source region and a drain region; and annealing the structure to diffuse phosphorous from the PSG into the silicon substrate to form a lightly doped source region and a lightly doped drain region in the silicon substrate below the PSG, said annealing step including heating the structure at a temperature of between 600° C. to 1,000° C. for between about 10 minutes and 60 minutes.
Claim 7
Independent Claim
244 words
A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of δ, comprising: preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a ferroelectric (FE) gate stack surround structure for surrounding a ferroelectric (FE) gate stack which is formed in a subsequent step, the step of forming a FE gate stack surround structure including depositing a layer of phosphorous silicate glass (PSG) on the substrate; and depositing an oxide layer over the PSG layer; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing, by CVD, oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2≧L1+2δ; depositing a first insulating layer over the structure; implanting arsenic ions to form a source region and a drain region; and annealing the structure to diffuse phosphorous from the PSG into the silicon substrate to form a lightly doped source region and a lightly doped drain region in the silicon substrate below the PSG, said annealing step including heating the structure at a temperature of between 600° C. to 1,000° C. for between about 10 minutes and 60 minutes.
Claim 8
Dependent Claim
61 words
The method of claim 5 wherein said step of forming the FE gate stack surround structure includes implanting phosphorous ions, at an energy level of 5 keV to 40 keV, and a concentration of 5.0×10 11 cm -2 to 1.0×10 13 cm -2 , to form an n- layer in the top 20 nm to 100 nm of the silicon substrate.
Claim 9
Dependent Claim
60 words
The method of claim 5 wherein said step of forming the FE gate stack includes depositing a bottom electrode to a thickness of between about 10 nm to 40 nm, depositing ferroelectric material to a thickness of between about 100 nm to 400 nm, and depositing a top electrode to a thickness of between about 10 nm to 40 nm.
Claim 10
Dependent Claim
29 words
The method of claim 7 wherein said steps of depositing the bottom and top electrodes include depositing material taken from the group consisting of Pt, Ir and Pt/Ir alloy.
Claim 11
Dependent Claim
51 words
The method of claim 7 wherein said step of depositing the ferroelectric material includes depositing a FE layer of material taken from the group consisting of Pb(Zr, Ti)O 3 (PZT), PLZT, SrBi 2 Ta 2 O 9 (SBT), Pb 5 Ge 3 O 11 , BaTiO 3 and LiNbO 3 .
Claim 12
Independent Claim
244 words
A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of δ, comprising: preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a ferroelectric (FE) gate stack surround structure for surrounding a ferroelectric (FE) gate stack which is formed in a subsequent step, the step of forming a FE gate stack surround structure including depositing a layer of phosphorous silicate glass (PSG) on the substrate; and depositing an oxide layer over the PSG layer; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing, by CVD, oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2≧L1+2δ; depositing a first insulating layer over the structure; implanting arsenic ions to form a source region and a drain region; and annealing the structure to diffuse phosphorous from the PSG into the silicon substrate to form a lightly doped source region and a lightly doped drain region in the silicon substrate below the PSG, said annealing step including heating the structure at a temperature of between 500° C. to 700° C. for between about 20 minutes and 100 minutes.
Claim 13
Independent Claim
244 words
A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of δ, comprising: preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a ferroelectric (FE) gate stack surround structure for surrounding a ferroelectric (FE) gate stack which is formed in a subsequent step, the step of forming a FE gate stack surround structure including depositing a layer of phosphorous silicate glass (PSG) on the substrate; and depositing an oxide layer over the PSG layer; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing, by CVD, oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2≧L1+2δ; depositing a first insulating layer over the structure; implanting arsenic ions to form a source region and a drain region; and annealing the structure to diffuse phosphorous from the PSG into the silicon substrate to form a lightly doped source region and a lightly doped drain region in the silicon substrate below the PSG, said annealing step including heating the structure at a temperature of between 500° C. to 700° C. for between about 20 minutes and 100 minutes.
Claim 14
Dependent Claim
61 words
The method of claim 10 wherein said step of forming the FE gate stack surround structure includes implanting phosphorous ions, at an energy level of 5 keV to 40 keV, and a concentration of 5.0×10 11 cm -2 to 1.0×10 13 cm -2 , to form an n- layer in the top 20 nm to 100 nm of the silicon substrate.
Claim 15
Dependent Claim
60 words
The method of claim 10 wherein said step of forming the FE gate stack includes depositing a bottom electrode to a thickness of between about 10 nm to 40 nm, depositing ferroelectric material to a thickness of between about 100 nm to 400 nm, and depositing a top electrode to a thickness of between about 10 nm to 40 nm.
Claim 16
Dependent Claim
29 words
The method of claim 12 wherein said steps of depositing the bottom and top electrodes include depositing material taken from the group consisting of Pt, Ir and Pt/Ir alloy.
Claim 17
Dependent Claim
51 words
The method of claim 12 wherein said step of depositing the ferroelectric material includes depositing a FE layer of material taken from the group consisting of Pb(Zr, Ti)O 3 (PZT), PLZT, SrBi 2 Ta 2 O 9 (SBT), Pb 5 Ge 3 O 11 , BaTiO 3 and LiNbO 3 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-04-11 | 2003-10-11 | 2004-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-04-11 | 2007-10-11 | 2008-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-04-11 | 2011-10-11 | 2012-04-11 | $7700.00 | Window Closed / Lapsed |