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US6043124A
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Method for forming high density nonvolatile memories with high capacitive-coupling ratio
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1998-03-13
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Granted: 2000-03-28
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Expires: 2018-03-13
Abstract
Abstract The present invention proposes a method for fabricating a high speed and high density nonvolatile memory cell. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited on the substrate and then the tunnel oxide region is defined by a standard photolithography process followed by an anisotropic etching. A high temperature steam oxidation process is used to grow a thick thermal oxide on the non-tunnel region. After removing the masking silicon nitride layer, the n+ impurity ions is implanted to form the source and drain, and a thermal annealing is performed to recover the implantation damage and to drive in the doped ions. Next, the pad oxide film is etched back and an ultra-thin undoped α-Si, or HSG-Si, film is deposited. A thermal oxidation process is carried out to convert the undoped α-Si or HSG-Si into textured tunnel oxide. Finally, the first n+ doped polysilicon film which serves as the floating gate, the interpoly dielectric such as ONO, the second n+ doped polysilicon film which serves as the control gate are sequentially formed, and the memory cell is finished.
Inventors
- 👤 Shye-Lin Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:48
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
203 words
A method for forming a nonvolatile memory cell with a textured tunnel oxide layer, said method comprising: forming a silicon oxide layer on a semiconductor substrate; forming a silicon nitride layer on said silicon oxide layer; patterning said silicon nitride layer to define tunnel oxide region and expose a portion of said silicon oxide which defines the non-tunnel region of said semiconductor substrate; performing a first thermal oxidation to oxidize a portion of said semiconductor substrate exposed by said silicon nitride, thereby generating a non-tunnel oxide on said semiconductor substrate; removing said silicon nitride layer; implanting ions into said semiconductor substrate to form a source and a drain using said non-tunnel oxide as a mask; performing an annealing to said semiconductor substrate and simultaneously driving said ions into said semiconductor substrate; removing said silicon oxide layer; forming a first polysilicon layer on said semiconductor substrate; performing a second thermal oxidation process to convert said first polysilicon layer into said textured tunnel oxide; forming a second polysilicon layer over said tunnel and non-tunnel oxides to serve as a floating gate; forming a dielectric layer on said floating gate; and forming a third polysilicon layer on said dielectric layer to serve as a control gate.
Claim 2
Independent Claim
203 words
A method for forming a nonvolatile memory cell with a textured tunnel oxide layer, said method comprising: forming a silicon oxide layer on a semiconductor substrate; forming a silicon nitride layer on said silicon oxide layer; patterning said silicon nitride layer to define tunnel oxide region and expose a portion of said silicon oxide which defines the non-tunnel region of said semiconductor substrate; performing a first thermal oxidation to oxidize a portion of said semiconductor substrate exposed by said silicon nitride, thereby generating a non-tunnel oxide on said semiconductor substrate; removing said silicon nitride layer; implanting ions into said semiconductor substrate to form a source and a drain using said non-tunnel oxide as a mask; performing an annealing to said semiconductor substrate and simultaneously driving said ions into said semiconductor substrate; removing said silicon oxide layer; forming a first polysilicon layer on said semiconductor substrate; performing a second thermal oxidation process to convert said first polysilicon layer into said textured tunnel oxide; forming a second polysilicon layer over said tunnel and non-tunnel oxides to serve as a floating gate; forming a dielectric layer on said floating gate; and forming a third polysilicon layer on said dielectric layer to serve as a control gate.
Claim 3
Dependent Claim
14 words
The method according to claim 1, wherein said semiconductor substrate is a p-type substrate.
Claim 4
Dependent Claim
17 words
The method according to claim 1, wherein said silicon oxide has a thickness of about 40-300 angstroms.
Claim 5
Dependent Claim
25 words
The method according to claim 1, wherein said first thermal oxidation is performed in an oxygen steam ambience at a temperature of about 800-1100° C.
Claim 6
Dependent Claim
17 words
The method according to claim 1, wherein said non-tunnel oxide has a thickness of about 300-2500 angstroms.
Claim 7
Dependent Claim
14 words
The method according to claim 1, wherein said implanted impurity ions are n-type ions.
Claim 8
Dependent Claim
13 words
The method according to claim 6, wherein said n-type ions are phosphorus ions.
Claim 9
Dependent Claim
13 words
The method according to claim 6, wherein said n-type ions are arsenic ions.
Claim 10
Dependent Claim
13 words
The method according to claim 6, wherein said n-type ions are antimony ions.
Claim 11
Dependent Claim
29 words
The method according to claim 6, wherein said n-type ions ions are implanted at about 0.5-150 -- keV with dosage of about 5×10 14 -5×10 16 atoms/cm 2 .
Claim 12
Dependent Claim
18 words
The method according to claim 1, wherein said annealing is performed at a temperature of about 800-1150° C.
Claim 13
Dependent Claim
38 words
The method according to claim 1, wherein said first polysilicon layer is formed by following method: depositing a amorphous silicon layer on said semiconductor substrate; performing a heating process to crystallize said amorphous silicon layer into polysilicon layer.
Claim 14
Dependent Claim
18 words
The method according to claim 12, wherein said amorphous silicon layer has a thickness of about 20-300 angstroms.
Claim 15
Dependent Claim
27 words
The method according to claim 12, wherein said heating process is performed in a N 2 ambience at the temperature raised from 25° C. to 950° C.
Claim 16
Dependent Claim
17 words
The method according to claim 12, wherein said polysilicon layer has a thickness of about 20-300 angstroms.
Claim 17
Dependent Claim
25 words
The method according to claim 1, wherein said second thermal oxidation is performed in a dry oxygen ambient at a temperature of about 750-1050° C.
Claim 18
Dependent Claim
17 words
The method according to claim 1, wherein said second polysilicon layer is formed of n-type doped polysilicon.
Claim 19
Dependent Claim
51 words
The method according to claim 1, wherein said dielectric layer is formed of the material selected from the group consisting of tantalum pentoxide (Ta 2 O 5 ), BST, a double film of silicon nitride and silicon oxide, and a triple film of silicon oxide, silicon nitride and silicon oxide (ONO).
Claim 20
Dependent Claim
17 words
The method according to claim 1, wherein said third polysilicon layer is formed of n-type doped polysilicon.
Claim 21
Independent Claim
204 words
A method for forming a nonvolatile memory cell with a textured tunnel oxide layer, said method comprising: forming a silicon oxide layer on a semiconductor substrate; forming a silicon nitride layer on said silicon oxide layer; patterning said silicon nitride layer to define tunnel oxide region and expose a portion of said silicon oxide which defines the non-tunnel region of said semiconductor substrate; performing a first thermal oxidation to oxidize a portion of said semiconductor substrate exposed by said silicon nitride, thereby generating a non-tunnel oxide on said semiconductor substrate; removing said silicon nitride layer; implanting ions into said semiconductor substrate to form a source and a drain using said non-tunnel oxide as a mask; performing an annealing to said semiconductor substrate and simultaneously driving said ions into said semiconductor substrate; removing said silicon oxide layer; forming a hemispherical grained silicon (HSG-silicon) layer on said semiconductor substrate; performing a second thermal oxidation process to convert said HSG-silicon layer into said textured tunnel oxide; forming a first polysilicon layer over said tunnel and non-tunnel oxides to serve as the floating gate forming a dielectric layer on said floating gate; and forming a second polysilicon layer on said dielectric layer to serve as the control gate.
Claim 22
Independent Claim
204 words
A method for forming a nonvolatile memory cell with a textured tunnel oxide layer, said method comprising: forming a silicon oxide layer on a semiconductor substrate; forming a silicon nitride layer on said silicon oxide layer; patterning said silicon nitride layer to define tunnel oxide region and expose a portion of said silicon oxide which defines the non-tunnel region of said semiconductor substrate; performing a first thermal oxidation to oxidize a portion of said semiconductor substrate exposed by said silicon nitride, thereby generating a non-tunnel oxide on said semiconductor substrate; removing said silicon nitride layer; implanting ions into said semiconductor substrate to form a source and a drain using said non-tunnel oxide as a mask; performing an annealing to said semiconductor substrate and simultaneously driving said ions into said semiconductor substrate; removing said silicon oxide layer; forming a hemispherical grained silicon (HSG-silicon) layer on said semiconductor substrate; performing a second thermal oxidation process to convert said HSG-silicon layer into said textured tunnel oxide; forming a first polysilicon layer over said tunnel and non-tunnel oxides to serve as the floating gate forming a dielectric layer on said floating gate; and forming a second polysilicon layer on said dielectric layer to serve as the control gate.
Claim 23
Dependent Claim
14 words
The method according to claim 20 wherein said semiconductor substrate is a p-type substrate.
Claim 24
Dependent Claim
17 words
The method according to claim 20, wherein said silicon oxide has a thickness of about 40-300 angstroms.
Claim 25
Dependent Claim
25 words
The method according to claim 20, wherein said first thermal oxidation is performed in an oxygen steam ambience at a temperature of about 800-1100° C.
Claim 26
Dependent Claim
17 words
The method according to claim 20, wherein said non-tunnel oxide has a thickness of about 300-2500 angstroms.
Claim 27
Dependent Claim
14 words
The method according to claim 20, wherein said implanted impurity ions are n-type ions.
Claim 28
Dependent Claim
13 words
The method according to claim 25, wherein said n-type ions are phosphoric ions.
Claim 29
Dependent Claim
13 words
The method according to claim 25, wherein said n-type ions are arsenic ions.
Claim 30
Dependent Claim
13 words
The method according to claim 25, wherein said n-type ions are antimony ions.
Claim 31
Dependent Claim
28 words
The method according to claim 25, wherein said n-type ions ions are implanted at about 0.5-150 keV with dosage of about 5×10 14 -5×10 16 atom/cm 2 .
Claim 32
Dependent Claim
18 words
The method according to claim 20, wherein said annealing is performed at a temperature of about 800-1150° C.
Claim 33
Dependent Claim
17 words
The method according to claim 20, wherein said HSG-silicon layer has a thickness of about 40-500 angstroms.
Claim 34
Dependent Claim
25 words
The method according to claim 20, wherein said second thermal oxidation is performed in a dry oxygen ambience at a temperature of about 750-1050° C.
Claim 35
Dependent Claim
17 words
The method according to claim 20, wherein said first polysilicon layer is formed of n-type doped polysilicon.
Claim 36
Dependent Claim
51 words
The method according to claim 20, wherein said dielectric layer is formed of the material selected from the group consisting of tantalum pentoxide (Ta 2 O 5 ), BST, a double film of silicon nitride and silicon oxide, and a triple film of silicon oxide, silicon nitride and silicon oxide (ONO).
Claim 37
Dependent Claim
17 words
The method according to claim 20, wherein said second polysilicon layer is formed of n-type doped polysilicon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-28 | 2003-09-27 | 2004-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-28 | 2007-09-27 | 2008-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-28 | 2011-09-27 | 2012-03-28 | $7700.00 | Window Closed / Lapsed |