US6028463A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable clock manager for a programmable logic device that can generate at least two different output clocks
Assignee: Agere Systems LLC
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Filing: 1997-10-15
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Granted: 2000-02-22
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Expires: 2017-10-15
Abstract
Abstract A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least two different output clocks having different clock rates. The different output clocks can be used to control different processes either within or outside the FPGA. For example, one output clock can be used to control the FPGA's input/output registers, while a second, faster output clock can be used to control the FPGA's internal registers.
Inventors
- 👤 Lucian R. Albu
- 👤 Barry K. Britton
- 👤 Wai-Bor Leung
- 👤 Richard G. Stuby, Jr.
- 👤 James A. Thompson
- 👤 Zeljko Zilic
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 01:39
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/1774; G; G06; G06F; G06F1/00; G06F1/04; G06F1/06; G06F1/08; H03K19/1733; H03K19/17704; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0816; H03L7/085; H03L7/089; H03L7/0891
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
70 words
A programmable logic device (PLD) having at least one programmable clock manager (PCM), the PCM comprising: (a) at least one input port configured to receive an input clock; (b) a PCM core function block programmably configurable to convert the input clock into at least two different output clocks having different programmable clock rates; and (c) at least two output ports configured to transmit the at least two different output clocks.
Claim 2
Dependent Claim
70 words
A programmable logic device (PLD) having at least one programmable clock manager (PCM), the PCM comprising: (a) at least one input port configured to receive an input clock; (b) a PCM core function block programmably configurable to convert the input clock into at least two different output clocks having different programmable clock rates; and (c) at least two output ports configured to transmit the at least two different output clocks.
Claim 3
Dependent Claim
15 words
The invention of claim 1, wherein the PLD is a field programmable gate array (FPGA).
Claim 4
Dependent Claim
34 words
The invention of claim 1, wherein a first output clock is used to drive processing internal to the PLD and a second output clock is used to drive input/output (I/O) operations for the PLD.
Claim 5
Dependent Claim
17 words
The invention of claim 3, wherein the first clock rate is higher than the second clock rate.
Claim 6
Dependent Claim
59 words
The invention of claim 1, wherein: the clock rate R O1 of a first output clock is given by: R.sub.O1= R.sub.I ·D0/D1 where R I is the clock rate of the input clock, and the clock rate R O2 of a second output clock is given by: R.sub.O2 =R.sub.O1 ·D2 where D0, D1, and D2 are independently programmable parameters.
Claim 7
Dependent Claim
20 words
The invention of claim 1, wherein the PCM is adapted to be programmed during PLD operations, without reconfiguring the PLD.
Claim 8
Dependent Claim
26 words
The invention of claim 1, wherein the PCM is adapted to be disabled to save power, when the input clock is not converted by the PCM.
Claim 9
Dependent Claim
62 words
The invention of claim 1, wherein the PCM can be configured to operate as a system component that is functionally independent of operations of the rest of the PLD, such that the PCM is adapted to be reset and/or reprogrammed without affecting the rest of the PLD, and the rest of the PLD can be reset and/or reprogrammed without affecting the PCM.
Claim 10
Dependent Claim
96 words
A programmable logic device (PLD) having at least one programmable clock manager (PCM), the PCM comprising: (a) at least one input port configured to receive an input clock; (b) a PCM core function block configured to convert the input clock into at least two different output clocks having different clock rates; and (c) at least two output ports configured to transmit the at least two different output clocks, wherein a first output clock is used to drive processing internal to the PLD and a second output clock is used to drive I/O operations for the PLD.
Claim 11
Dependent Claim
96 words
A programmable logic device (PLD) having at least one programmable clock manager (PCM), the PCM comprising: (a) at least one input port configured to receive an input clock; (b) a PCM core function block configured to convert the input clock into at least two different output clocks having different clock rates; and (c) at least two output ports configured to transmit the at least two different output clocks, wherein a first output clock is used to drive processing internal to the PLD and a second output clock is used to drive I/O operations for the PLD.
Claim 12
Dependent Claim
17 words
The invention of claim 9, wherein the first clock rate is higher than the second clock rate.
Claim 13
Dependent Claim
59 words
The invention of claim 9, wherein: the clock rate R O1 of the first output clock is given by: R.sub.O1 =R.sub.I D0/D1 where R I is the clock rate of the input clock; and the clock rate R O2 of the second output clock is given by: R.sub.O2 =R.sub.O1 ·D2 where D0, D1, and D2 are independently programmable parameters.
Claim 14
Dependent Claim
20 words
The invention of claim 9, wherein the PCM is adapted to be programmed during PLD operations, without reconfiguring the PLD.
Claim 15
Dependent Claim
26 words
The invention of claim 9, wherein the PCM is adapted to be disabled to save power, when the input clock is not converted by the PCM.
Claim 16
Dependent Claim
62 words
The invention of claim 9, wherein the PCM can be configured to operate as a system component that is functionally independent of operations of the rest of the PLD, such that the PCM is adapted to be reset and/or reprogrammed without affecting the rest of the PLD, and the rest of the PLD can be reset and/or reprogrammed without affecting the PCM.
Claim 17
Dependent Claim
160 words
The invention of claim 9, wherein: the first clock rate is higher than the second clock rate; the clock rate R O1 of the first output clock is given by: R.sub.O1 =R.sub.I ·D0/D1 where R I is the clock rate of the input clock; the clock rate R O2 of the second output clock is given by: R.sub.O2 =R.sub.O1 ·D2 where D0, D1, and D2 are independently programmable parameters; the PCM is adapted to be programmed during PLD operations, without reconfiguring the PLD; the PCM is adapted to be disabled to save power, when the input clock is not converted by the PCM; and the PCM can be configured to operate as a system component that is functionally independent of operations of the rest of the PLD, such that the PCM is adapted to be reset and/or reprogrammed without affecting the rest of the PLD, and the rest of the PLD can be reset and/or reprogrammed without affecting the PCM.
Claim 18
Dependent Claim
122 words
A programmable logic device (PLD) having at least one programmable clock manager (PCM), the PCM comprising: (a) at least one input port configured to receive an input clock; (b) a PCM core function block configured to convert the input clock into at least two different output clocks having different clock rates; and (c) at least two output ports configured to transmit the at least two different output clocks, wherein: the clock rate R O1 of a first output clock is given by: R.sub.O1 =R.sub.I ·D0/D1 where R I is the clock rate of the input clock; and the clock rate R O2 of a second output clock is given by: R.sub.O2 =R.sub.O1 ·D2 where D0, D1, and D2 are independently programmable parameters.
Claim 19
Dependent Claim
122 words
A programmable logic device (PLD) having at least one programmable clock manager (PCM), the PCM comprising: (a) at least one input port configured to receive an input clock; (b) a PCM core function block configured to convert the input clock into at least two different output clocks having different clock rates; and (c) at least two output ports configured to transmit the at least two different output clocks, wherein: the clock rate R O1 of a first output clock is given by: R.sub.O1 =R.sub.I ·D0/D1 where R I is the clock rate of the input clock; and the clock rate R O2 of a second output clock is given by: R.sub.O2 =R.sub.O1 ·D2 where D0, D1, and D2 are independently programmable parameters.
Claim 20
Dependent Claim
20 words
The invention of claim 16, wherein the PCM is adapted to be programmed during PLD operations, without reconfiguring the PLD.
Claim 21
Dependent Claim
26 words
The invention of claim 16, wherein the PCM is adapted to be disabled to save power, when the input clock is not converted by the PCM.
Claim 22
Dependent Claim
62 words
The invention of claim 16, wherein the PCM can be configured to operate as a system component that is functionally independent of operations of the rest of the PLD, such that the PCM is adapted to be reset and/or reprogrammed without affecting the rest of the PLD, and the rest of the PLD can be reset and/or reprogrammed without affecting the PCM.
Claim 23
Dependent Claim
83 words
A programmable logic device (PLD) having at least one programmable clock manager (PCM), the PCM comprising: (a) at least one input port configured to receive an input clock; (b) a PCM core function block configured to convert the input clock into at least two different output clocks having different clock rates; and (c) at least two output ports configured to transmit the at least two different output clocks, wherein the PCM is adapted to be programmed during PLD operations, without reconfiguring the PLD.
Claim 24
Dependent Claim
83 words
A programmable logic device (PLD) having at least one programmable clock manager (PCM), the PCM comprising: (a) at least one input port configured to receive an input clock; (b) a PCM core function block configured to convert the input clock into at least two different output clocks having different clock rates; and (c) at least two output ports configured to transmit the at least two different output clocks, wherein the PCM is adapted to be programmed during PLD operations, without reconfiguring the PLD.
Claim 25
Dependent Claim
26 words
The invention of claim 20, wherein the PCM is adapted to be disabled to save power, when the input clock is not converted by the PCM.
Claim 26
Dependent Claim
62 words
The invention of claim 20, wherein the PCM can be configured to operate as a system component that is functionally independent of operations of the rest of the PLD, such that the PCM is adapted to be reset and/or reprogrammed without affecting the rest of the PLD, and the rest of the PLD can be reset and/or reprogrammed without affecting the PCM.
Claim 27
Dependent Claim
140 words
A programmable logic device (PLD) having at least one programmable clock manager (PCM), the PCM comprising: (a) at least one input port configured to receive an input clock; (b) a PCM core function block configured to convert the input clock into at least two different output clocks having different clock rates; and (c) at least two output ports configured to transmit the at least two different output clocks, wherein the PCM is adapted to be programmed during PLD operations, without reconfiguring the PLD, wherein the PCM can be configured to operate as a system component that is functionally independent of operations of the rest of the PLD, such that the PCM is adapted to be reset and/or reprogrammed without affecting the rest of the PLD, and the rest of the PLD can be reset and/or reprogrammed without affecting the PCM.
Claim 28
Dependent Claim
140 words
A programmable logic device (PLD) having at least one programmable clock manager (PCM), the PCM comprising: (a) at least one input port configured to receive an input clock; (b) a PCM core function block configured to convert the input clock into at least two different output clocks having different clock rates; and (c) at least two output ports configured to transmit the at least two different output clocks, wherein the PCM is adapted to be programmed during PLD operations, without reconfiguring the PLD, wherein the PCM can be configured to operate as a system component that is functionally independent of operations of the rest of the PLD, such that the PCM is adapted to be reset and/or reprogrammed without affecting the rest of the PLD, and the rest of the PLD can be reset and/or reprogrammed without affecting the PCM.
Claim 29
Dependent Claim
26 words
The invention of claim 23, wherein the PCM is adapted to be disabled to save power, when the input clock is not converted by the PCM.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-21 | 2003-08-23 | 2004-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-21 | 2007-08-23 | 2008-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-21 | 2011-08-23 | 2012-02-22 | $7700.00 | Window Closed / Lapsed |