US6027980A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming a decoupling capacitor
Assignee: Intel Corp
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Filing: 1997-04-28
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Granted: 2000-02-22
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Expires: 2017-04-28
Abstract
Abstract A decoupling capacitor incorporated into an integrated circuit. The capacitor is disposed over a first region of a substrate comprising electronic circuitry, and not over a second region of the substrate. The capacitor comprises a lower and an upper conductive layer separated by an interposing insulative layer. An additional insulative layer is disposed beneath the lower conductive layer while another insulative layer is disposed above the upper conductive layer, and the capacitor provides capacitance for the electronic circuitry.
Inventors
- 👤 Donald S. Gardner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:47
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/601; H10W20/00; H10W20/01; H10W20/071; H10W20/074; H10W20/076; H10W20/081; H10W20/083; H10W20/40; H10W20/41; H10W20/42; H10W20/423; H10W20/435; H10W20/495; H10W20/496
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
147 words
A process for forming a capacitor on a substrate having circuitry, the process comprising the steps of: depositing a first insulative layer on said substrate; depositing a first conductive layer on said first insulative layer; depositing a second insulative layer on said first conductive layer; depositing a second conductive layer on said second insulative layer; forming a patterning layer on a first region of said substrate, leaving a second region of said substrate exposed; removing said second conductive layer, said second insulative layer, said first conductive layer and said first insulative layer from said second region; depositing a third insulative layer on said first and said second regions; forming openings in said third insulative layer in said first and said second regions; depositing a third conductive layer in said openings; and depositing an upper level conductive layer on said third insulative layer and said third conductive layer.
Claim 2
Dependent Claim
147 words
A process for forming a capacitor on a substrate having circuitry, the process comprising the steps of: depositing a first insulative layer on said substrate; depositing a first conductive layer on said first insulative layer; depositing a second insulative layer on said first conductive layer; depositing a second conductive layer on said second insulative layer; forming a patterning layer on a first region of said substrate, leaving a second region of said substrate exposed; removing said second conductive layer, said second insulative layer, said first conductive layer and said first insulative layer from said second region; depositing a third insulative layer on said first and said second regions; forming openings in said third insulative layer in said first and said second regions; depositing a third conductive layer in said openings; and depositing an upper level conductive layer on said third insulative layer and said third conductive layer.
Claim 3
Dependent Claim
26 words
The process as described in claim 1 wherein said steps of depositing said third conductive layer and depositing said upper level conductive layer are performed simultaneously.
Claim 4
Dependent Claim
42 words
The process as described in claim 1 further comprising the steps of: depositing an etch-stop layer on said third insulative layer prior to forming said patterning layer; and etching said etch-stop layer from said first region subsequent to forming said patterning layer.
Claim 5
Dependent Claim
24 words
The process as described in claim 3 wherein said etch-stop layer comprises a material selected from the group consisting of silicon and silicon nitride.
Claim 6
Dependent Claim
132 words
A process for forming a capacitor on a substrate having circuitry comprising the steps of: depositing a first insulative layer on said substrate; depositing a first conductive layer on said first insulative layer; depositing a second insulative layer on said first conductive layer; depositing a second conductive layer on said second insulative layer; forming a patterning layer on a first region of said substrate, leaving exposed a second region of said substrate; removing said second conductive layer from said second region; depositing a third insulative layer on said first and said second regions; forming openings in said third insulative layer in said first and said second regions; depositing a third conductive layer in said openings; and depositing an upper level conductive layer on said third insulative layer and said third conductive layer.
Claim 7
Dependent Claim
132 words
A process for forming a capacitor on a substrate having circuitry comprising the steps of: depositing a first insulative layer on said substrate; depositing a first conductive layer on said first insulative layer; depositing a second insulative layer on said first conductive layer; depositing a second conductive layer on said second insulative layer; forming a patterning layer on a first region of said substrate, leaving exposed a second region of said substrate; removing said second conductive layer from said second region; depositing a third insulative layer on said first and said second regions; forming openings in said third insulative layer in said first and said second regions; depositing a third conductive layer in said openings; and depositing an upper level conductive layer on said third insulative layer and said third conductive layer.
Claim 8
Dependent Claim
42 words
The process as described in claim 5 further comprising the steps of: depositing an etch-stop layer on said third insulative layer prior to forming said patterning layer; and etching said etch-stop layer from said first region subsequent to forming said patterning layer.
Claim 9
Dependent Claim
24 words
The process as described in claim 6 wherein said etch-stop layer comprises a material selected from the group consisting of silicon and silicon nitride.
Claim 10
Dependent Claim
26 words
The process as described in claim 5 wherein said first conductive layer is disposed in a portion of said second region and comprises a ground plane.
Claim 11
Dependent Claim
28 words
The process as described in claim 8 wherein said ground plane is disposed in a portion of said second region having an interconnect line to carry a signal.
Claim 12
Dependent Claim
17 words
The process as described in claim 5 wherein said first conductive layer comprises a power distribution level.
Claim 13
Dependent Claim
54 words
The process as described in claim 5 wherein said first conductive layer is patterned prior to said step of depositing a second insulative layer, such that said first conductive layer is removed from a portion of said first region, said second conductive layer comprising a ground plane in said portion of said first region.
Claim 14
Dependent Claim
26 words
The process as described in claim 8 wherein said portion of said first region having said ground plane comprises an interconnect line to carry a signal.
References Cited (Backward Citations)
US4023197A
Cited
US4931411A
Cited
US4628406A
Cited
US4855953A
Cited
US5165166A
Cited
US4803450A
Cited
US5079670A
Cited
US5006481A
Cited
US5056216A
Cited
US5210379A
Cited
US5104822A
Cited
US5262596A
Cited
US5119154A
Cited
US5126794A
Cited
US5139971A
Cited
US5308929A
Cited
US5414221A
Cited
US5472900A
Cited
US5583739A
Cited
US5691229A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-21 | 2003-08-23 | 2004-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-21 | 2007-08-23 | 2008-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-21 | 2011-08-23 | 2012-02-22 | $7700.00 | Window Closed / Lapsed |