US4023197A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit chip carrier and method for forming the same
Assignee: International Business Machines Corp
•
Filing: 1975-06-25
•
Granted: 1977-05-10
•
Expires: 1995-06-25
Abstract
Abstract An integrated circuit chip carrier with multi-level metallurgy, in which the effects of the metallurgy in causing elevation irregularities at the various levels of the structure are minimized, is produced by a method wherein a first plurality of levels of metallization patterns respectively separated by layers of dielectric material are first formed on a planar primary layer supported on a temporary substrate having a chemical etchability different from that of the layer. The primary layer is electrically insulative with respect to said metallization patterns. Then, a supporting layer is formed on the uppermost covering layer, after which the substrate is removed with a chemical etchant which preferentially etches the substrate away from the insulative layer. Next, an opposite plurality of levels of metallization patterns are formed on the side of the insulative layer opposite to the first formed metallization patterns. These opposite metallization patterns are also respectively separated by covering layers of dielectric material.
Inventors
- 👤 Ingrid E. Magdo
- 👤 Steven Magdo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 04:09
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/67; H10W70/68; H10W70/685; H10W99/00; H10W72/00; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/20; H10W72/251; H10W72/252
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
203 words
An integrated circuit chip carrier comprising an insulative layer of dielectric material having a first planar surface and an opposite planar surface a first level metallization pattern formed on said first planar surface, a first covering layer of dielectric material over said metallization pattern and said first surface, said first covering layer having elevated portions corresponding to said first metallization pattern, at least one additional level metallization pattern on said first covering layer, an additional covering layer of dielectric material over each additional level metallization pattern, said additional covering layer having elevated portions corresponding to the underlying metallization patterns, an opposite level metallization pattern formed on said opposite planar surface, an opposite covering layer of dielectric material over said opposite level metallization pattern and said opposite surface, said opposite covering layer having elevated portions corresponding to said opposite level metallization pattern, at least one additional opposite level metallization pattern on said opposite covering layer, an additional opposite covering layer of dielectric material over each additional opposite level metallization pattern, said additional opposite covering layer having elevated portions corresponding to underlying opposite level metallization patterns, and a base member forming an interface with the surface of said additional covering layer for supporting the carrier.
Claim 2
Dependent Claim
203 words
An integrated circuit chip carrier comprising an insulative layer of dielectric material having a first planar surface and an opposite planar surface a first level metallization pattern formed on said first planar surface, a first covering layer of dielectric material over said metallization pattern and said first surface, said first covering layer having elevated portions corresponding to said first metallization pattern, at least one additional level metallization pattern on said first covering layer, an additional covering layer of dielectric material over each additional level metallization pattern, said additional covering layer having elevated portions corresponding to the underlying metallization patterns, an opposite level metallization pattern formed on said opposite planar surface, an opposite covering layer of dielectric material over said opposite level metallization pattern and said opposite surface, said opposite covering layer having elevated portions corresponding to said opposite level metallization pattern, at least one additional opposite level metallization pattern on said opposite covering layer, an additional opposite covering layer of dielectric material over each additional opposite level metallization pattern, said additional opposite covering layer having elevated portions corresponding to underlying opposite level metallization patterns, and a base member forming an interface with the surface of said additional covering layer for supporting the carrier.
Claim 3
Dependent Claim
17 words
The integrated circuit carrier of claim 1 wherein said base is a layer of polycrystalline semiconductor material.
Claim 4
Dependent Claim
42 words
The integrated circuit chip carrier of claim 2 wherein at least one of the covering layers has a plurality of via holes formed therethrough and metal in said via holes forming conductive paths between the metallization patterns separated by said covering layer.
Claim 5
Dependent Claim
47 words
The integrated circuit chip carrier of claim 3 wherein at least one of the covering layers over the first planar surface and at least one of the covering layers over the opposite planar surface, each has a plurality of said via holes and said metallic conductive paths.
Claim 6
Dependent Claim
40 words
The integrated circuit chip carrier of claim 4 wherein said insulative layer has at least one via hole formed therethrough and metal in said via hole forms a conductive path between said first level and said opposite level metallization patterns.
Claim 7
Dependent Claim
26 words
The integrated circuit chip carrier of claim 5 wherein at least one of the via holes is coincident with a via hole through an underlying layer.
Claim 8
Dependent Claim
63 words
The integrated circuit chip carrier of claim 5 wherein said additional covering layer has a plurality of via holes formed therethrough to the underlying metallization pattern, and, said carrier further includes a plurality of solder pads having a lower melting point than said underlying metallization pattern on the surface of said additional covering layer conductively connected to said pattern through said via holes.
Claim 9
Dependent Claim
34 words
The carrier of claim 7 further including at least one integrated circuit chip having a plurality of solder pads corresponding to and bonded to the solder pads on the carrier by solder reflow joints.
Claim 10
Dependent Claim
15 words
The integrated circuit chip carrier of claim 5 wherein said supporting layer is polycrystalline silicon.
Claim 11
Dependent Claim
60 words
The chip carrier of claim 9 wherein said polycrystalline silicon layer is doped with conductivity-determining impurities to render it conductive, and the covering layer beneath said polycrystalline silicon layer has at least one via hole formed therethrough and polycrystalline silicon in said via hole forming a conductive path from said polycrystalline layer to the metallization pattern underlying said covering layer.
Claim 12
Dependent Claim
16 words
The integrated circuit chip carrier of claim 9 wherein said covering layers are of silicon dioxide.
Claim 13
Dependent Claim
15 words
The integrated circuit chip carrier of claim 11 wherein said insulative layer is silicon dioxide.
Claim 14
Dependent Claim
43 words
The integrated circuit chip carrier of claim 12 wherein said insulative layer is a composite comprising a silicon dioxide layer providing said first planar surface, a silicon dioxide layer providing said opposite planar surface and a metallic layer intermediate said silicon dioxide layers.
Claim 15
Dependent Claim
67 words
The integrated circuit chip carrier of claim 4 wherein said insulative layer and said opposite covering layer have formed therethrough at least one via hole passing through both of said layers and spaced from said opposite level metallization pattern and metal in said via hole forming a conductive path between said first level metallization pattern and the additional opposite level metallization pattern on said opposite covering layer.
References Cited (Backward Citations)
US3622384A
Cited
US3936865A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-05-09 | 1980-11-08 | 1981-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-05-09 | 1984-11-08 | 1985-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-05-09 | 1988-11-08 | 1989-05-10 | $7700.00 | Window Closed / Lapsed |