US6025259A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dual damascene process using high selectivity boundary layers
Assignee: GlobalFoundries Inc
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Filing: 1998-07-02
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Granted: 2000-02-15
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Expires: 2018-07-02
Abstract
Abstract A method of manufacturing a semiconductor device with multiple dual damascene structures that maintains the maximum density. A first dual damascene structure having a first via and a first trench is formed in a first interlayer dielectric and a first etch stop layer formed on the planarized surface of the first interlayer dielectric. Two layers of interlayer dielectric separated by a second etch stop layer is formed on the surface of the first etch stop layer. A third etch stop layer is formed on the upper layer of interlayer dielectric and a first photoresist layer formed on the third etch stop layer. The photoresist layer is etched having a dimension coinciding with a width dimension of the first via. The third etch stop layer is selectively etched and the first photoresist layer removed and replaced by a second photoresist layer. The second photoresist layer is etched having a dimension coinciding with a width dimension of the first trench. The two layers of interlayer dielectric and the first, second and third etch stop layers are etched to form a second dual damascene structure having a second via and a second trench having the same dimensions as the first dual damascene structure.
Inventors
- 👤 Allen S. Yu
- 👤 Paul J. Steffan
- 👤 Thomas Charles Scholer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:45
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/084; H10W20/087; H10W20/088
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
443 words
A method of manufacturing a semiconductor device, the method comprising: forming a first layer of interlayer dielectric on a surface of a semiconductor substrate that contains active semiconductor devices; forming a first via having a width W 1 in the first layer of interlayer dielectric; forming a first trench having a width W 2 in the first layer of interlayer dielectric wherein the first via and the first trench form a first dual damnascene structure; planarizing a surface of the first layer of interlayer dielectric and forming a first etch stop layer on the planarized surface of the first layer of interlayer dielectric; forming a second layer of interlayer dielectric on a surface of the first etch stop layer; planarizing a surface of the second layer of interlayer dielectric and forming a second etch stop layer on the planarized surface of the second layer of interlayer dielectric; forming a third layer of interlayer dielectric on a surface of the second etch stop layer; planarizing a surface of the third layer of interlayer dielectric and forming a third etch stop layer on the planarized surface of the third interlayer dielectric; forming a first layer of photoresist on a surface of the third etch stop layer and etching the first layer of photoresist with a pattern having a width dimension of W 1 ; selectively etching a portion of the third etch stop layer exposed by the step of etching the first layer of photoresist, wherein the portion of the third etch stop layer is etched down to the planarized surface of the third layer of interlayer dielectric; removing the first layer of photoresist and forming a second layer of photoresist on the semiconductor device and etching the second layer of photoresist with a pattern having a width dimension of W 2 exposing a portion of the third etch stop layer and a portion of the third layer of interlayer dielectric; selectively etching the portion of the third layer of interlayer dielectric down to the second etch stop layer, wherein a portion of the second etch stop layer is exposed; selectively etching the exposed portion of the second etch stop layer down to the second layer of interlayer dielectric, wherein a portion of the second layer of interlayer dielectric is exposed; selectively etching the portion of the second layer of interlayer dielectric down to the first etch stop layer, wherein a portion of the first etch stop layer is exposed; and selectively etching the exposed portion of the first etch stop layer, selectively etching the exposed portion of the second etch stop layer and selectively etching the exposed portion of the third etch stop layer.
Claim 2
Independent Claim
443 words
A method of manufacturing a semiconductor device, the method comprising: forming a first layer of interlayer dielectric on a surface of a semiconductor substrate that contains active semiconductor devices; forming a first via having a width W 1 in the first layer of interlayer dielectric; forming a first trench having a width W 2 in the first layer of interlayer dielectric wherein the first via and the first trench form a first dual damnascene structure; planarizing a surface of the first layer of interlayer dielectric and forming a first etch stop layer on the planarized surface of the first layer of interlayer dielectric; forming a second layer of interlayer dielectric on a surface of the first etch stop layer; planarizing a surface of the second layer of interlayer dielectric and forming a second etch stop layer on the planarized surface of the second layer of interlayer dielectric; forming a third layer of interlayer dielectric on a surface of the second etch stop layer; planarizing a surface of the third layer of interlayer dielectric and forming a third etch stop layer on the planarized surface of the third interlayer dielectric; forming a first layer of photoresist on a surface of the third etch stop layer and etching the first layer of photoresist with a pattern having a width dimension of W 1 ; selectively etching a portion of the third etch stop layer exposed by the step of etching the first layer of photoresist, wherein the portion of the third etch stop layer is etched down to the planarized surface of the third layer of interlayer dielectric; removing the first layer of photoresist and forming a second layer of photoresist on the semiconductor device and etching the second layer of photoresist with a pattern having a width dimension of W 2 exposing a portion of the third etch stop layer and a portion of the third layer of interlayer dielectric; selectively etching the portion of the third layer of interlayer dielectric down to the second etch stop layer, wherein a portion of the second etch stop layer is exposed; selectively etching the exposed portion of the second etch stop layer down to the second layer of interlayer dielectric, wherein a portion of the second layer of interlayer dielectric is exposed; selectively etching the portion of the second layer of interlayer dielectric down to the first etch stop layer, wherein a portion of the first etch stop layer is exposed; and selectively etching the exposed portion of the first etch stop layer, selectively etching the exposed portion of the second etch stop layer and selectively etching the exposed portion of the third etch stop layer.
Claim 3
Dependent Claim
35 words
The method of claim 1 further comprising forming a barrier layer on walls formed by etching the first etch stop layer, the second interlayer dielectric, the second etch stop layer and the third interlayer dielectric.
Claim 4
Dependent Claim
59 words
The method of claim 2 further comprising filling the etched portions of the first etch stop layer, the second interlayer dielectric, the second etch stop layer and the third interlayer dielectric with a conductive material wherein a second dual damascene structure is formed and wherein the second dual damascene structure is in contact with the first dual damascene structure.
Claim 5
Dependent Claim
20 words
The method of claim 3 wherein the conductive material is selected from the group consisting of aluminum, tungsten and copper.
Claim 6
Dependent Claim
28 words
The method of claim 4 wherein the etch stop layers are formed from a material selected from the group consisting of SiON, Si 3 N 4 and TaN.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-14 | 2003-08-16 | 2004-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-14 | 2007-08-16 | 2008-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-14 | 2011-08-16 | 2012-02-15 | $7700.00 | Window Closed / Lapsed |