US6023192A
Expired / Lapsed
US
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Dual gain amplifier circuit
Assignee: STMicroelectronics SA
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Filing: 1998-10-09
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Granted: 2000-02-08
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Expires: 2018-10-09
Abstract
Abstract A dual gain amplifier provides separate gains so that the amplifier's input characteristics are unaffected by the gain selected. The dual gain amplifier comprises a first input amplifier and a third amplifier connected in cascade, and a second input amplifier and a fourth amplifier connected in cascade. A first LC circuit is connected in parallel to a second LC circuit which are both connected to the third amplifier. Likewise, a third LC circuit is connected in parallel to a fourth LC circuit which are connected to the fourth amplifier. The first and third LC circuits have a first quality factor and the second and fourth LC circuits have a second quality factor. The dual gain amplifier switches from a first state in which only the first and third LC circuits conduct to a second state in which all four LC circuits conduct.
Inventors
- 👤 Belot Didier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 04:48
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/72; H03F3/189; H03F3/19; H03F3/191; H03F3/45; H03F3/45071; H03F3/45076; H03F3/4508; H03F3/45085; H03F3/45089; H03J; H03J5/00; H03J5/24; H03J5/246; H03F2203/00; H03F2203/45; H03F2203/45024; H03F2203/45198; H03F2203/45256; H03F2203/45386; H03F2203/45394; H03F2203/45641; H03F2203/45704; H03F2203/45722; H03F2203/45726
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
133 words
A dual gain amplifier comprising: a first input amplifier; a second input amplifier; a third amplifier coupled to the first input amplifier for forming a first cascaded circuit; a fourth amplifier coupled to the second input amplifier for forming a second cascaded circuit; a first LC circuit and second LC circuit connected in parallel and to said third amplifier; a third LC circuit and fourth LC circuit connected in parallel and to said fourth amplifier; the first and third LC circuits having a first quality factor, and the second and fourth LC circuits having a second quality factor; and means for switching the dual gain amplifier from a first state in which only the first and third LC circuits are conducting to a second state in which all four LC circuits are conducting.
Claim 2
Dependent Claim
133 words
A dual gain amplifier comprising: a first input amplifier; a second input amplifier; a third amplifier coupled to the first input amplifier for forming a first cascaded circuit; a fourth amplifier coupled to the second input amplifier for forming a second cascaded circuit; a first LC circuit and second LC circuit connected in parallel and to said third amplifier; a third LC circuit and fourth LC circuit connected in parallel and to said fourth amplifier; the first and third LC circuits having a first quality factor, and the second and fourth LC circuits having a second quality factor; and means for switching the dual gain amplifier from a first state in which only the first and third LC circuits are conducting to a second state in which all four LC circuits are conducting.
Claim 3
Dependent Claim
28 words
A dual gain amplifier according to claim 1, wherein each of the second and fourth LC circuits comprises: an inductor; and a silicon substrate portion mounting said inductor.
Claim 4
Dependent Claim
22 words
A dual gain amplifier according to claim 1, wherein each of the third and fourth amplifiers comprises at least one bipolar transistor.
Claim 5
Dependent Claim
22 words
A dual gain amplifier according to claim 1, wherein each of the third and fourth amplifiers comprises at least one MOS transistor.
Claim 6
Dependent Claim
18 words
A dual gain amplifier according to claim 1, wherein the first quality factor is greater than about 4.5.
Claim 7
Dependent Claim
18 words
A dual gain amplifier according to claim 1, wherein the second quality factor is less than about 2.5.
Claim 8
Dependent Claim
31 words
A dual gain amplifier according to claim 1, wherein the means for switching the dual gain amplifier between a first and second state comprises a first and a second MOS transistor.
Claim 9
Dependent Claim
139 words
A dual gain amplifier comprising: a first input amplifier; a second input amplifier; a third amplifier coupled to the first input amplifier for forming a first cascaded circuit; a fourth amplifier coupled to the second input amplifier for forming a second cascaded circuit; a first LC circuit and second LC circuit connected in parallel and to said third amplifier; a third LC circuit and fourth LC circuit connected in parallel and to said fourth amplifier; the first and third LC circuits having a first quality factor and the second and fourth LC circuits having a second quality factor less than the first quality factor; and means for switching the dual gain amplifier from a first state in which only the first and third LC circuits are conducting to a second state in which all four LC circuits are conducting.
Claim 10
Dependent Claim
139 words
A dual gain amplifier comprising: a first input amplifier; a second input amplifier; a third amplifier coupled to the first input amplifier for forming a first cascaded circuit; a fourth amplifier coupled to the second input amplifier for forming a second cascaded circuit; a first LC circuit and second LC circuit connected in parallel and to said third amplifier; a third LC circuit and fourth LC circuit connected in parallel and to said fourth amplifier; the first and third LC circuits having a first quality factor and the second and fourth LC circuits having a second quality factor less than the first quality factor; and means for switching the dual gain amplifier from a first state in which only the first and third LC circuits are conducting to a second state in which all four LC circuits are conducting.
Claim 11
Dependent Claim
28 words
A dual gain amplifier according to claim 8, wherein each of the second and fourth LC circuits comprises: an inductor; and a silicon substrate portion mounting said inductor.
Claim 12
Dependent Claim
22 words
A dual gain amplifier according to claim 8, wherein each of the third and fourth amplifiers comprises at least one bipolar transistor.
Claim 13
Dependent Claim
22 words
A dual gain amplifier according to claim 8, wherein each of the third and fourth amplifiers comprises at least one MOS transistor.
Claim 14
Dependent Claim
18 words
A dual gain amplifier according to claim 8, wherein the first quality factor is greater than about 4.5.
Claim 15
Dependent Claim
18 words
A dual gain amplifier according to claim 8, wherein the second quality factor is less than about 2.5.
Claim 16
Dependent Claim
31 words
A dual gain amplifier according to claim 8, wherein the means for switching said dual gain amplifier between a first and second state comprises a first and a second MOS transistor.
Claim 17
Dependent Claim
157 words
A dual gain amplifier comprising: a first input amplifier; a second input amplifier; a third amplifier coupled to the first input amplifier for forming a first cascaded circuit; a fourth amplifier coupled to the second input amplifier for forming a second cascaded circuit; a first LC circuit and second LC circuit connected in parallel and to said third amplifier; a third LC circuit and fourth LC circuit connected in parallel and to said fourth amplifier; the second and fourth LC circuits each comprises an inductor, and a silicon substrate portion mounting said inductor; the first and third LC circuits having a first quality factor and the second and fourth LC circuits having a second quality factor less than the first quality factor; and means for switching the dual gain amplifier from a first state in which only the first and third LC circuits are conducting to a second state in which all four LC circuits are conducting.
Claim 18
Dependent Claim
157 words
A dual gain amplifier comprising: a first input amplifier; a second input amplifier; a third amplifier coupled to the first input amplifier for forming a first cascaded circuit; a fourth amplifier coupled to the second input amplifier for forming a second cascaded circuit; a first LC circuit and second LC circuit connected in parallel and to said third amplifier; a third LC circuit and fourth LC circuit connected in parallel and to said fourth amplifier; the second and fourth LC circuits each comprises an inductor, and a silicon substrate portion mounting said inductor; the first and third LC circuits having a first quality factor and the second and fourth LC circuits having a second quality factor less than the first quality factor; and means for switching the dual gain amplifier from a first state in which only the first and third LC circuits are conducting to a second state in which all four LC circuits are conducting.
Claim 19
Dependent Claim
22 words
A dual gain amplifier according to claim 15, wherein each of the third and fourth amplifiers comprises at least one bipolar transistor.
Claim 20
Dependent Claim
22 words
A dual gain amplifier according to claim 15, wherein each of the third and fourth amplifiers comprises at least one MOS transistor.
Claim 21
Dependent Claim
18 words
A dual gain amplifier according to claim 15, wherein the first quality factor is greater than about 4.5.
Claim 22
Dependent Claim
18 words
A dual gain amplifier according to claim 15, wherein the second quality factor is less than about 2.5.
Claim 23
Dependent Claim
31 words
A dual gain amplifier according to claim 15, wherein the means for switching said dual gain amplifier between a first and second state comprises a first and a second MOS transistor.
Claim 24
Independent Claim
141 words
A method for providing a dual gain amplifier, comprising the steps of: forming a first input amplifier; forming a third amplifier coupled to the first input amplifier; forming a second input amplifier; forming a fourth amplifier coupled to the second input amplifier; connecting a first and second LC circuit in parallel and to the third amplifier; connecting a third and fourth LC circuit in parallel and to the fourth amplifier; selecting a first quality factor for the first and third LC circuits and selecting a second quality factor for the second and fourth LC circuits so that the first quality factor is greater than the second quality factor; and switching said dual gain amplifier from a first state in which only the first and third LC circuits are conducting to a second state in which all four LC circuits are conducting.
Claim 25
Independent Claim
141 words
A method for providing a dual gain amplifier, comprising the steps of: forming a first input amplifier; forming a third amplifier coupled to the first input amplifier; forming a second input amplifier; forming a fourth amplifier coupled to the second input amplifier; connecting a first and second LC circuit in parallel and to the third amplifier; connecting a third and fourth LC circuit in parallel and to the fourth amplifier; selecting a first quality factor for the first and third LC circuits and selecting a second quality factor for the second and fourth LC circuits so that the first quality factor is greater than the second quality factor; and switching said dual gain amplifier from a first state in which only the first and third LC circuits are conducting to a second state in which all four LC circuits are conducting.
Claim 26
Dependent Claim
27 words
A method according to claim 21, further comprising the steps of mounting an inductor of each of the second and fourth LC circuits on a silicon substrate.
Claim 27
Dependent Claim
25 words
A method according to claim 21, further comprising the step of forming at least one bipolar transistor for each of the third and fourth amplifiers.
Claim 28
Dependent Claim
25 words
A method according to claim 21, further comprising the step of forming at least one MOS transistor for each of the third and fourth amplifiers.
Claim 29
Dependent Claim
21 words
A method according to claim 21, wherein the first quality factor is selected so that it is greater than about 4.5.
Claim 30
Dependent Claim
21 words
A method according to claim 21, wherein the second quality factor is selected so that it is less than about 2.5.
Claim 31
Dependent Claim
23 words
A method according to claim 21, wherein the step of switching comprises switching between a first MOS transistor and a second MOS transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-07 | 2003-08-09 | 2004-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-07 | 2007-08-09 | 2008-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-07 | 2011-08-09 | 2012-02-08 | $7700.00 | Window Closed / Lapsed |