Core cell structure and corresponding process for NAND-type high performance flash memory device

Claim 2

A NAND-type flash memory device, comprising: a core region comprising a stacked gate flash memory cell structure and a select gate transistor; and a periphery region comprising a low voltage transistor and a high voltage transistor, wherein the select gate transistor and the low voltage transistor both have a gate oxide layer and a gate electrode layer, wherein a thickness of the gate oxide layer of the select gate transistor and the low voltage transistor are substantially the same, and a thickness of the gate electrode layer of the select gate transistor and the low voltage transistor are substantially the same.

Claim 3

The NAND-type flash memory device of claim 1, wherein the gate oxide layer is about 160 Å.

Claim 4

The NAND-type flash memory device of claim 1, wherein the stacked gate flash memory cell comprises: a tunnel oxide layer; a floating gate layer overlying the tunnel oxide layer; an insulating layer overlying the floating gate layer; and a control gate layer overlying the insulating layer.

Claim 5

The NAND-type flash memory device of claim 1, wherein the high voltage transistor has a structure comprising a gate oxide layer of about 400 A and a conductive gate region overlying the gate oxide layer.

Claim 6

The NAND-type flash memory device of claim 1, wherein the select gate transistor has a channel stop implant region.

Claim 7

The NAND-type flash memory device of claim 1, further comprising a plurality of select gate transistors, wherein the plurality of select gate transistors share a common conductive gate region to thereby form a select gate word line.

Claim 8

A NAND-type flash memory device, comprising: a core region comprising a stacked gate flash memory cell structure having a thin oxide material forming a tunnel oxide layer, a first conductive material forming a poly1 layer overlying the tunnel oxide layer, an insulating material forming an insulating layer overlying the poly1 layer and a second conductive material forming a poly2 layer overlying the insulating layer; the core region further comprising a select gate transistor having a gate oxide material forming a gate oxide layer and the second conductive material forming a gate layer overlying the gate oxide layer; and a periphery region including a low voltage transistor and a high voltage transistor, wherein the same gate oxide formation step used to form the gate oxide layer of the select gate transistor also forms a gate oxide laver of the low voltage transistor and thus a thickness of the gate oxide layers of the select gate transistor and the low voltage transistor are substantially the same.

Claim 9

A NAND-type flash memory device, comprising: a core region comprising a stacked gate flash memory cell structure having a thin oxide material forming a tunnel oxide layer, a first conductive material forming a poly1 layer overlying the tunnel oxide layer, an insulating material forming an insulating layer overlying the poly1 layer and a second conductive material forming a poly2 layer overlying the insulating layer; the core region further comprising a select gate transistor having a gate oxide material forming a gate oxide layer and the second conductive material forming a gate layer overlying the gate oxide layer; and a periphery region including a low voltage transistor and a high voltage transistor, wherein the same gate oxide formation step used to form the gate oxide layer of the select gate transistor also forms a gate oxide laver of the low voltage transistor and thus a thickness of the gate oxide layers of the select gate transistor and the low voltage transistor are substantially the same.