US6022758A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for manufacturing solder leads on a semiconductor device package
Assignee: Adeia Semiconductor Technologies LLC
•
Filing: 1995-07-07
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Granted: 2000-02-08
•
Expires: 2015-07-07
Abstract
Abstract A process of forming a packaged integrated circuit by aperturing a discrete packaging layer attached on a silicon substrate. A plurality of solder leads are formed on the layer. Electrical connections are formed from the leads to pads on the substrate.
Inventors
- 👤 Pierre Badehi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:30
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10W72/01; H10W72/012; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W72/20; H10W72/241; H10W72/244; H10W72/251; H10W72/252; H10W72/29; H10W72/921; H10W72/922
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
116 words
A method of forming a packaged integrated circuit comprising: providing a silicon substrate; forming at least one metal layer onto said silicon substrate including a plurality of pads; providing a discrete packaging layer; aperturing the discrete packaging layer to provide an apertured discrete packaging layer having apertures located in locations corresponding to locations of said plurality of pads; attaching said apertured discrete packaging layer over said at least one metal layer so that said apertures communicate with said pads; forming a plurality of solder leads on an exterior surface of said at least one packaging layer; and forming electrical connections directly from individual ones of said plurality of pads to individual ones of said solder leads.
Claim 2
Independent Claim
116 words
A method of forming a packaged integrated circuit comprising: providing a silicon substrate; forming at least one metal layer onto said silicon substrate including a plurality of pads; providing a discrete packaging layer; aperturing the discrete packaging layer to provide an apertured discrete packaging layer having apertures located in locations corresponding to locations of said plurality of pads; attaching said apertured discrete packaging layer over said at least one metal layer so that said apertures communicate with said pads; forming a plurality of solder leads on an exterior surface of said at least one packaging layer; and forming electrical connections directly from individual ones of said plurality of pads to individual ones of said solder leads.
Claim 3
Dependent Claim
25 words
A method according to claim 1 and wherein said electrical connections are formed following attachment of said at least one packaging layer to said substrate.
Claim 4
Dependent Claim
70 words
A method according to claim 1 and wherein said steps of: forming at least one metal layer, attaching at least one packaging layer over said at least one metal layer, forming a plurality of solder leads on an exterior surface of said at least one packaging layer and forming electrical connections directly from individual ones of said plurality of pads to individual ones of solder leads are carried out waferwise.
Claim 5
Dependent Claim
70 words
A method according to claim 1 and wherein said steps of: forming at least one metal layer, attaching at least one packaging layer over said at least one metal layer, forming a plurality of solder leads on an exterior surface of said at least one packaging layer and forming electrical connections directly from individual ones of said plurality of pads to individual ones of solder leads are carried out diewise.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-07 | 2003-08-09 | 2004-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-07 | 2007-08-09 | 2008-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-07 | 2011-08-09 | 2012-02-08 | $7700.00 | Window Closed / Lapsed |