Patent US4030416A successfully refreshed from Google Patents.
Patent US6021067A successfully refreshed from Google Patents.
US6021067A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit of sensing a fuse cell in a flash memory
Assignee: SK Hynix Inc
•
Filing: 1998-12-11
•
Granted: 2000-02-01
•
Expires: 2018-12-11
Abstract
Abstract This invention discloses a circuit of sensing a fuse cell used for repairing a failed memory cell, the circuit comprising a power-on reset circuit to generate reset pulses at the time of power-on of the flash memory, a reference circuit to latch an initial state according to output signal of the power-on reset circuit, a voltage divider circuit to output the voltage for sensing a fuse cell in said reference circuit according to output signal of the reference circuit, and a main memory cell data latch circuit to latch information on the fuse cell according to output signals of the power-on reset circuit and the reference circuit.
Inventors
- 👤 Chang Wan Ha
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:20
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/20; G11C7/00; G11C7/06; G11C7/067
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
110 words
A circuit of sensing a fuse cell in a flash memory, comprising: a power-on resist circuit to generate a reset pulse at the time of power-on of the flash memory; a reference circuit to latch an initial state according to an output signal of said power-on reset circuit, said reference circuit comprising said fuse cell; a voltage divider circuit to output the voltage for sensing said fuse cell in said reference circuit according to an output signal of said reference circuit; and a main memory cell data latch circuit to latch information on said fuse cell according to said output signals of said power-on reset circuit and said reference circuit.
Claim 2
Dependent Claim
110 words
A circuit of sensing a fuse cell in a flash memory, comprising: a power-on resist circuit to generate a reset pulse at the time of power-on of the flash memory; a reference circuit to latch an initial state according to an output signal of said power-on reset circuit, said reference circuit comprising said fuse cell; a voltage divider circuit to output the voltage for sensing said fuse cell in said reference circuit according to an output signal of said reference circuit; and a main memory cell data latch circuit to latch information on said fuse cell according to said output signals of said power-on reset circuit and said reference circuit.
Claim 3
Dependent Claim
51 words
The circuit of claim 1, wherein said reference circuit comprises: an initializing circuit to initialize said latch circuit according to said output signal of said power-on reset circuit; and a delay circuit to delay an output or said latch circuit and to control said fuse cell and said voltage divider circuit.
Claim 4
Dependent Claim
42 words
The circuit of claim 2, wherein said sensing circuit comprises: a pair of NMOS transistors connected between said latch circuit and said fuse cell in series and to which output of said power-on reset circuit and said voltage divider circuit are input.
Claim 5
Dependent Claim
23 words
The circuit of claim 2, wherein said latch circuit comprises a pair of inverters connected between said initializing circuit and said sensing circuit.
Claim 6
Dependent Claim
66 words
The circuit of claim 2, wherein said initializing circuit comprises; a PMOS transistor which is connected between said latch circuit and a power terminal and to which an output of said power-on reset circuit is input; and a NMOS transistor which is connected between said latch circuit and a grounded terminal and to which an output of said power-on reset circuit is input through an inverter.
Claim 7
Dependent Claim
178 words
A circuit of sensing a fuse cell in a flash memory, comprising: a power-on resist circuit to generate a reset pulse at the time of power-on of the flash memory; a reference circuit to latch an initial state according to an output signal of said power-on reset circuit, said reference circuit comprising said fuse cell, a sensing circuit to sense data on said fuse cell, a latch circuit to latch data of said fuse cell which are sensed by said sensing circuit, an initializing circuit to initialize said latch circuit according to said output signal of said power-on reset circuit and a delay circuit to delay an output of said latch circuit and to control said fuse cell and said voltage divider circuit; a voltage divider circuit to output the voltage for sensing a fuse cell in said reference circuit according to an output signal of said reference circuit; and a main memory cell data latch circuit to latch information on said fuse cell according to said output signals of said power-on reset circuit and said reference circuit.
Claim 8
Dependent Claim
178 words
A circuit of sensing a fuse cell in a flash memory, comprising: a power-on resist circuit to generate a reset pulse at the time of power-on of the flash memory; a reference circuit to latch an initial state according to an output signal of said power-on reset circuit, said reference circuit comprising said fuse cell, a sensing circuit to sense data on said fuse cell, a latch circuit to latch data of said fuse cell which are sensed by said sensing circuit, an initializing circuit to initialize said latch circuit according to said output signal of said power-on reset circuit and a delay circuit to delay an output of said latch circuit and to control said fuse cell and said voltage divider circuit; a voltage divider circuit to output the voltage for sensing a fuse cell in said reference circuit according to an output signal of said reference circuit; and a main memory cell data latch circuit to latch information on said fuse cell according to said output signals of said power-on reset circuit and said reference circuit.
Claim 9
Dependent Claim
42 words
The circuit of claim 6, wherein said sensing circuit comprises: a pair of NMOS transistors connected between said latch circuit and said fuse cell in series and to which output of said power-on reset circuit and said voltage divider circuit are input.
Claim 10
Dependent Claim
23 words
The circuit of claim 6, wherein said latch circuit comprises a pair of inverters connected between said initializing circuit and said sensing circuit.
Claim 11
Dependent Claim
64 words
The circuit of claim 6, wherein said initializing circuit comprises: a PMOS transistor which is connected between said latch circuit and a power terminal and to which output of said power-on reset circuit is input; and an NMOS transistor which is connected between said latch circuit and a grounded terminal and to which output of said power-on reset circuit is input through an inverter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-31 | 2003-08-02 | 2004-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-31 | 2007-08-02 | 2008-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-31 | 2011-08-02 | 2012-02-01 | $7700.00 | Window Closed / Lapsed |