Semiconductor memory having redundancy memory decoder circuit

Claim 1

A semiconductor memory having a redundancy decoder circuit, said decoder circuit comprising: an output line; a precharge circuit for precharging said output line in response to a precharge signal; a plurality of first transistors provided correspondingly to a plurality of address signals and coupled between said output line and a first power line; a fuse provided controllably to be blown or not; a latch circuit coupled to said fuse to produce a control signal which takes a first logic level when said fuse is blown and a second logic level when said fuse is not blown; and a second transistor coupled between said output line and said first power line and controlled by said control signal, wherein said fuse is connected between a second power line and a first node and said latch circuit includes a third transistor connected between said first power line and said first node and an invertor having an input node connected to said first node and an output node connected to gates of said second and third transistors, and wherein said precharge circuit includes a fourth transistor coupled between said output line and said second power line and a gate circuit allowing said fourth transistor to respond to said precharge signal when said fuse is not blown and rendering said fourth transistor non-connective when said fuse is blown.