US5327384A
Expired / Lapsed
US
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Flash memory
Assignee: NEC Corp
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Filing: 1992-12-28
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Granted: 1994-07-05
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Expires: 2012-12-28
Abstract
Abstract A flash memory of the present invention has a comparator for inspecting whether or not data is erased from each memory cell. If data written in each of all the memory cells has been erased completely, erasing operation to the memory cell block is prohibitted.
Inventors
- 👤 Kazuhisa Ninomiya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:28
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/344; G11C16/3445; G11C16/10; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
135 words
A flash memory, having a memory region divided into a plurality of memory blocks each having a plurality of memory cells, comprising: means for erasing data written in each memory cell of any one of said memory cell blocks which is selected to be erased; means for inspecting whether or not data is erased from each memory cell of each memory cell block, and for generating a control signal when data written of all of the memory cells of the memory cell block are erased completely; and means for controlling said data erasing means in accordance with said control signal to prohibit the erasing operation to said memory cell block in which all the data have been erased, said means for controlling said data erasing means comprising a flip-flop circuit for latching said control signal.
Claim 2
Dependent Claim
135 words
A flash memory, having a memory region divided into a plurality of memory blocks each having a plurality of memory cells, comprising: means for erasing data written in each memory cell of any one of said memory cell blocks which is selected to be erased; means for inspecting whether or not data is erased from each memory cell of each memory cell block, and for generating a control signal when data written of all of the memory cells of the memory cell block are erased completely; and means for controlling said data erasing means in accordance with said control signal to prohibit the erasing operation to said memory cell block in which all the data have been erased, said means for controlling said data erasing means comprising a flip-flop circuit for latching said control signal.
Claim 3
Dependent Claim
139 words
A flash memory, having a memory region divided into a plurality of memory blocks each having a plurality of memory cells, comprising: means for erasing data written in each memory cell of any one of said memory cell blocks which is selected to be erased; means for inspecting whether or not data is erased from each memory cell of each memory cell block, and for generating a control signal when data written in all of the memory cells of the memory cell block are erased completely, and means for controlling said data erasing means in accordance with said control signal to prohibit the erasing operation to said memory cell block in which all the data have been erased said means for controlling said data erasing means comprising an electrically erasable non-volatile semiconductor memory device for latching said control signal.
Claim 4
Dependent Claim
139 words
A flash memory, having a memory region divided into a plurality of memory blocks each having a plurality of memory cells, comprising: means for erasing data written in each memory cell of any one of said memory cell blocks which is selected to be erased; means for inspecting whether or not data is erased from each memory cell of each memory cell block, and for generating a control signal when data written in all of the memory cells of the memory cell block are erased completely, and means for controlling said data erasing means in accordance with said control signal to prohibit the erasing operation to said memory cell block in which all the data have been erased said means for controlling said data erasing means comprising an electrically erasable non-volatile semiconductor memory device for latching said control signal.
Claim 5
Dependent Claim
223 words
A flash memory, having a memory region divided into a plurality of memory blocks each having a plurality of memory cells comprising; means for erasing data written in each memory cell of any one of said memory cell blocks which is selected to be erased; means for inspecting whether or not data is erased from each memory cell of each memory cell block, and for generating a control signal when data written in all of the memory cells of the memory cell block are erased completely; means for controlling said data erasing means in accordance with said control signal to prohibit the erasing operation of said memory cell block in which all the data have been erased; means for writing a pre-program data into each of said memory cells of said selected memory cell block before an erasing operation of the memory cell block is carried out; and means for inspecting whether or not said pre-program data is written into all of the memory cells in each of said selected memory cell blocks, and for generating a write completion signal to said controlling means; wherein said controlling means controls said data erasing means in accordance with said write completion signal to start the erasing operation to said memory cell block in which said pre-program data is written in each of all memory cells.
Claim 6
Dependent Claim
223 words
A flash memory, having a memory region divided into a plurality of memory blocks each having a plurality of memory cells comprising; means for erasing data written in each memory cell of any one of said memory cell blocks which is selected to be erased; means for inspecting whether or not data is erased from each memory cell of each memory cell block, and for generating a control signal when data written in all of the memory cells of the memory cell block are erased completely; means for controlling said data erasing means in accordance with said control signal to prohibit the erasing operation of said memory cell block in which all the data have been erased; means for writing a pre-program data into each of said memory cells of said selected memory cell block before an erasing operation of the memory cell block is carried out; and means for inspecting whether or not said pre-program data is written into all of the memory cells in each of said selected memory cell blocks, and for generating a write completion signal to said controlling means; wherein said controlling means controls said data erasing means in accordance with said write completion signal to start the erasing operation to said memory cell block in which said pre-program data is written in each of all memory cells.
Claim 7
Dependent Claim
25 words
A flash memory, according to claim 3, wherein; said means for controlling said data erasing means comprises a flip-flop circuit for latching said control signal.
Claim 8
Dependent Claim
139 words
A flash memory, having a memory region divided into a plurality of memory blocks each having a plurality of memory cells comprising; means for erasing data written in each memory cell of any one of said memory cell blocks which is selected to be erased; means for inspecting whether or not data is erased from each memory cell of each memory cell block, and for generating a control signal when data written in all of the memory cells of the memory cell block are erased completely; means for controlling said data erasing means in accordance with said control signal to prohibit the erasing operation of said memory cell block in which all the data have been erased, and said means for controlling said data erasing means comprising an electrically erasable non-volatile semiconductor memory device for latching said control signal.
Claim 9
Dependent Claim
139 words
A flash memory, having a memory region divided into a plurality of memory blocks each having a plurality of memory cells comprising; means for erasing data written in each memory cell of any one of said memory cell blocks which is selected to be erased; means for inspecting whether or not data is erased from each memory cell of each memory cell block, and for generating a control signal when data written in all of the memory cells of the memory cell block are erased completely; means for controlling said data erasing means in accordance with said control signal to prohibit the erasing operation of said memory cell block in which all the data have been erased, and said means for controlling said data erasing means comprising an electrically erasable non-volatile semiconductor memory device for latching said control signal.
Claim 10
Dependent Claim
238 words
A flash memory, having a memory region divided into a plurality of memory blocks each having a plurality of memory cells comprising; means for erasing data written in each memory cell of said memory cell blocks which is selected to be erased; means for inspecting whether or not data is erased from each memory cell of each memory cell block, and for generating a control signal when data written in all of the memory cells of the memory cell block are erased completely, said control signal generating means comprising an electrically erasable non-volatile semiconductor memory device for latching said control signal; means for controlling said data erasing means in accordance with said control signal to prohibit the erasing operation of said memory cell block in which all the data have been erased; means for writing a pre-program data into each of said memory cells of said selected memory cell block before an erasing operation of the memory cell block is carried out; means for inspecting whether or not said pre-program data is written into all of the memory cells in each of said selected memory cell blocks, and for generating a write completion signal to said controlling means; and wherein said controlling means controls said data erasing means in accordance with said write completion signal to start the erasing operation of said memory cell block in which said pre-program data is written in each of all memory cells.
Claim 11
Dependent Claim
238 words
A flash memory, having a memory region divided into a plurality of memory blocks each having a plurality of memory cells comprising; means for erasing data written in each memory cell of said memory cell blocks which is selected to be erased; means for inspecting whether or not data is erased from each memory cell of each memory cell block, and for generating a control signal when data written in all of the memory cells of the memory cell block are erased completely, said control signal generating means comprising an electrically erasable non-volatile semiconductor memory device for latching said control signal; means for controlling said data erasing means in accordance with said control signal to prohibit the erasing operation of said memory cell block in which all the data have been erased; means for writing a pre-program data into each of said memory cells of said selected memory cell block before an erasing operation of the memory cell block is carried out; means for inspecting whether or not said pre-program data is written into all of the memory cells in each of said selected memory cell blocks, and for generating a write completion signal to said controlling means; and wherein said controlling means controls said data erasing means in accordance with said write completion signal to start the erasing operation of said memory cell block in which said pre-program data is written in each of all memory cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-04 | 1998-01-03 | 1998-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-04 | 2002-01-03 | 2002-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-04 | 2006-01-03 | 2006-07-05 | $7700.00 | Window Closed / Lapsed |