Semiconductor device in which thin silicon portions are formed by electrochemical stop etching method

Claim 2

A semiconductor device comprising: a first conductivity type semiconductor substrate in which a reduced thickness region is formed; a second conductivity type semiconductor layer disposed on said first conductivity type semiconductor substrate; circuit wiring disposed on said second conductivity type semiconductor layer, a pair of wiring lines of said circuit wiring that are closest to each other being separated by a first distance; and etching wiring contacting said semiconductor layer at a region where said reduced thickness region is located thereunder, said etching wiring being utilized for applying an etching voltage to said region during formation of said reduced thickness region, wherein a minimum distance between said etching wiring and said circuit wiring is defined by a second distance greater than said first distance.

Claim 3

A semiconductor device according to claim 1 further comprising: a chip region disposed on said second conductivity type semiconductor layer, said circuit wiring formed on said chip region; and an isolating layer surrounding said chip region.

Claim 4

A semiconductor device according to claim 2, wherein said chip region has an integrated circuit element region to which said circuit wiring is connected.

Claim 5

A semiconductor device according to claim 3, wherein said second distance is four to ten times greater than said first distance.

Claim 6

A semiconductor device according to claim 4, wherein said etching wiring and said circuit wiring are made of metal.

Claim 7

A semiconductor device according to claim 1, wherein a member of said circuit wiring that is nearest to said etching wiring is connected to said first conductivity type substrate.

Claim 8

A semiconductor device according to claim 6 further comprising: a chip region disposed on said second conductivity type semiconductor layer, said circuit wring formed on said chip region; and an isolating layer surrounding said chip region.

Claim 9

A semiconductor device according to claim 7, wherein said second distance is four to ten times greater than said first distance.

Claim 10

A semiconductor device according to claim 8, wherein said etching wiring and said circuit wiring are made of metal.

Claim 11

A semiconductor device according to claim 1, wherein said etching wiring and said circuit wiring are disposed on an insulating film.

Claim 12

A semiconductor device according to claim 10 further comprising: a chip region disposed on said second conductivity type semiconductor layer, said circuit wring formed on said chip region; and an isolating layer surrounding said chip region.

Claim 13

A semiconductor device according to claim 11, wherein said second distance is four to ten times greater than said first distance.

Claim 14

A semiconductor device according to claim 12, wherein said etching wiring and said circuit wiring are made of metal.

Claim 15

A semiconductor device according to claim 1, wherein said second distance is four times or more greater than said first distance.

Claim 16

A semiconductor device according to claim 14, wherein said etching wiring and said circuit wiring are made of metal.

Claim 17

A semiconductor device according to claim 14, wherein said second is up to ten times greater than said first distance.

Claim 18

A semiconductor device according to claim 16, wherein said etching wiring and said circuit wiring are made of metal.

Claim 19

A semiconductor device according to claim 2, further comprising: a branch wiring member branched from said etching wiring in said chip region; and an inspection pad connected to said branch wiring member for receiving a voltage to detect a junction leakage current between said first conductivity type semiconductor substrate and said second conductivity type semiconductor layer.

Claim 20

A semiconductor device according to claim 18, wherein said branch wiring member is made of the same material as that of said etching wiring.

Claim 21

A semiconductor device according to claim 19, wherein said branch wiring member is covered with a protective insulating film and said inspection pad is exposed in an opening of said protective insulating film.

Claim 22

A semiconductor device according to claim 2, further comprising: an additional wiring member connected to said reduced thickness region and disposed in said chip region at a position different from that of said etching wiring; and an inspection pad connected to said additional wiring member for receiving a voltage to detect a junction leakage current between said first conductivity type semiconductor substrate and said second conductivity type semiconductor layer.

Claim 23

A semiconductor device according to claim 21, wherein said additional wiring member is made of the same material as that of said etching wiring.

Claim 24

A semiconductor device according to claim 22, wherein said additional wiring member is covered with a protective insulating film and said inspection pad is exposed in an opening of said protective insulating film.

Claim 25

A semicoductor device comprising: a first conductivity type semiconductor substrate in which a reduced thickness region is formed; a second conductivity type semiconductor layer disposed on said first conductivity type semiconductor substrate; a circuit wiring disposed on said second conductivity type semiconductor layer, a pair of wiring lines of said circuit wiring that are closest to each other being separated by a first distance; etching wiring connected to said semiconductor layer at a region where said reduced thickness region is located thereunder, said etching wiring being utilized for applying an etching voltage to said region during formation of said reduced thickness region; a chip region disposed on said second conductivity type semiconductor layer, said circuit wiring being disposed in said chip region; a branch wiring member branched from said etching wiring in said chip region; and an inspection pad connected to said branch wiring member for receiving a voltage to detect the amount of junction leakage current between said first conductivity type semiconductor substrate and said second conductivity type semiconductor layer.

Claim 26

A semicoductor device comprising: a first conductivity type semiconductor substrate in which a reduced thickness region is formed; a second conductivity type semiconductor layer disposed on said first conductivity type semiconductor substrate; a circuit wiring disposed on said second conductivity type semiconductor layer, a pair of wiring lines of said circuit wiring that are closest to each other being separated by a first distance; etching wiring connected to said semiconductor layer at a region where said reduced thickness region is located thereunder, said etching wiring being utilized for applying an etching voltage to said region during formation of said reduced thickness region; a chip region disposed on said second conductivity type semiconductor layer, said circuit wiring being disposed in said chip region; a branch wiring member branched from said etching wiring in said chip region; and an inspection pad connected to said branch wiring member for receiving a voltage to detect the amount of junction leakage current between said first conductivity type semiconductor substrate and said second conductivity type semiconductor layer.

Claim 27

A semiconductor device according to claim 24, wherein said branch wiring member is made of the same material as said etching wiring.

Claim 28

A semiconductor device according to claim 25, wherein said branch wiring member is covered with a protective insulating film and said inspection pad is exposed in an opening of said protective insulating film.

Claim 29

A semiconductor device comprising: a first conductivity type semiconductor substrate in which a reduced thickness region is formed; a second conductivity type semiconductor layer disposed on said first conductivity type semiconductor substrate; a circuit wiring disposed on said second conductivity type semiconductor layer, a pair of wiring lines of said circuit wiring that are closest to each other being separated by a first distance; etching wiring connected to said semiconductor layer at a region where said reduced thickness region is located thereunder, said etching wiring being utilized for applying an etching voltage to said region during formation of said reduced thickness region; a chip region disposed on said second conductivity type semiconductor layer, said circuit wiring being disposed in said chip region; an additional wiring member connected to said reduced thickness region and disposed in said chip region at a position different from that of said etching wiring; and an inspection pad connected to said additional wiring member for receiving a voltage to detect a junction leakage current between said first conductivity type semiconductor substrate and said second conductivity type semiconductor layer.

Claim 30

A semiconductor device comprising: a first conductivity type semiconductor substrate in which a reduced thickness region is formed; a second conductivity type semiconductor layer disposed on said first conductivity type semiconductor substrate; a circuit wiring disposed on said second conductivity type semiconductor layer, a pair of wiring lines of said circuit wiring that are closest to each other being separated by a first distance; etching wiring connected to said semiconductor layer at a region where said reduced thickness region is located thereunder, said etching wiring being utilized for applying an etching voltage to said region during formation of said reduced thickness region; a chip region disposed on said second conductivity type semiconductor layer, said circuit wiring being disposed in said chip region; an additional wiring member connected to said reduced thickness region and disposed in said chip region at a position different from that of said etching wiring; and an inspection pad connected to said additional wiring member for receiving a voltage to detect a junction leakage current between said first conductivity type semiconductor substrate and said second conductivity type semiconductor layer.

Claim 31

A semiconductor device according to claim 27 wherein said additional wiring member is made of the same material as said etching wiring.

Claim 32

A semiconductor device according to claim 28, wherein said additional wiring member is covered with a protective insulating film and said inspection pad is exposed in an opening of said protective insulating film.

Claim 33

A semiconductor device comprising: a first conductivity type semiconductor substrate in which a reduced thickness region is formed; a second conductivity type semiconductor layer disposed on said first conductivity type semiconductor substrate; circuit wiring disposed on said second conductivity type semiconductor layer, a pair of wiring lines of said circuit wiring that are closest to each other being separated by a first distance; etching wiring connected to said semiconductor layer at a region where said reduced thickness region is located thereunder, said etching wiring being utilized for applying an etching voltage to said region during formation of said reduced thickness region, a chip region disposed on said second conductivity type semiconductor layer, said circuit wiring formed on said chip region; an isolating layer surrounding said chip region, a branch wiring member branched from said etching wiring in said chip region; and an inspection pad connected to said branch wiring member for receiving a voltage to detect ajunction leakage current between said first conductivity type semiconductor substrate and said second conductivity type semiconductor layer, wherein a minimum distance between said etching wiring and said circuit wiring is defined by a second distance greater than said first distance.

Claim 34

A semiconductor device comprising: a first conductivity type semiconductor substrate in which a reduced thickness region is formed; a second conductivity type semiconductor layer disposed on said first conductivity type semiconductor substrate; circuit wiring disposed on said second conductivity type semiconductor layer, a pair of wiring lines of said circuit wiring that are closest to each other being separated by a first distance; etching wiring connected to said semiconductor layer at a region where said reduced thickness region is located thereunder, said etching wiring being utilized for applying an etching voltage to said region during formation of said reduced thickness region, a chip region disposed on said second conductivity type semiconductor layer, said circuit wiring formed on said chip region; an isolating layer surrounding said chip region, a branch wiring member branched from said etching wiring in said chip region; and an inspection pad connected to said branch wiring member for receiving a voltage to detect ajunction leakage current between said first conductivity type semiconductor substrate and said second conductivity type semiconductor layer, wherein a minimum distance between said etching wiring and said circuit wiring is defined by a second distance greater than said first distance.

Claim 35

A semiconductor device comprising: a first conductivity type semiconductor substrate in which a reduced thickness region is formed; a second conductivity type semiconductor layer disposed on said first conductivity type semiconductor substrate; circuit wiring disposed on said second conductivity type semiconductor layer, a pair of wiring lines of said circuit wiring that are closest to each other being separated by a first distance; etching wiring connected to said semiconductor layer at a region where said reduced thickness region is located thereunder, said etching wiring being utilized for applying an etching voltage to said region during formation of said reduced thickness region, a chip region disposed on said second conductivity type semiconductor layer, said circuit wring formed on said chip region; an isolating layer surrounding said chip region, an additional wiring member connected to said reduced thickness region and disposed in said chip region at a position different from that of said etching wiring; and an inspection pad connected to said additional wiring member for receiving a voltage to detect a junction leakage current between said first conductivity type semiconductor substrate and said second conductivity type semiconductor layer, wherein a minimum distance between said etching wiring and said circuit wiring is defined by a second distance greater than said first distance.

Claim 36

A semiconductor device comprising: a first conductivity type semiconductor substrate in which a reduced thickness region is formed; a second conductivity type semiconductor layer disposed on said first conductivity type semiconductor substrate; circuit wiring disposed on said second conductivity type semiconductor layer, a pair of wiring lines of said circuit wiring that are closest to each other being separated by a first distance; etching wiring connected to said semiconductor layer at a region where said reduced thickness region is located thereunder, said etching wiring being utilized for applying an etching voltage to said region during formation of said reduced thickness region, a chip region disposed on said second conductivity type semiconductor layer, said circuit wring formed on said chip region; an isolating layer surrounding said chip region, an additional wiring member connected to said reduced thickness region and disposed in said chip region at a position different from that of said etching wiring; and an inspection pad connected to said additional wiring member for receiving a voltage to detect a junction leakage current between said first conductivity type semiconductor substrate and said second conductivity type semiconductor layer, wherein a minimum distance between said etching wiring and said circuit wiring is defined by a second distance greater than said first distance.

Claim 37

A semiconductor device comprising: a first conductivity type semiconductor substrate in which reduced thickness regions are formed and a second conductivity type semiconductor layer disposed on said first conductivity type semiconductor substrate, said substrate being composed of a plurality of chip patterns, each containing at least one reduced thickness region, and a plurality of scribe regions between said chip patterns; circuit wiring disposed on said second conductivity type semiconductor layer in each said chip pattern, a pair of wiring lines of said circuit wiring that are closest to each other being separated by a first distance in each said chip pattern; and etching wiring contacting said semiconductor layer at etching wiring regions where said reduced thickness regions are located thereunder, said etching wiring being utilized for applying an etching voltage to said etching wiring regions during formation of said reduced thickness regions, wherein a minimum distance between said etching wiring and said circuit wiring in each said chip pattern is defined by a second distance greater than said first distance.

Claim 38

A semiconductor device comprising: a first conductivity type semiconductor substrate in which reduced thickness regions are formed and a second conductivity type semiconductor layer disposed on said first conductivity type semiconductor substrate, said substrate being composed of a plurality of chip patterns, each containing at least one reduced thickness region, and a plurality of scribe regions between said chip patterns; circuit wiring disposed on said second conductivity type semiconductor layer in each said chip pattern, a pair of wiring lines of said circuit wiring that are closest to each other being separated by a first distance in each said chip pattern; and etching wiring contacting said semiconductor layer at etching wiring regions where said reduced thickness regions are located thereunder, said etching wiring being utilized for applying an etching voltage to said etching wiring regions during formation of said reduced thickness regions, wherein a minimum distance between said etching wiring and said circuit wiring in each said chip pattern is defined by a second distance greater than said first distance.