Patent US6014758A successfully refreshed from Google Patents.
US6014758A
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Method and apparatus for detecting and reporting failed processor reset
Assignee: Intel Corp
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Filing: 1997-09-18
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Granted: 2000-01-11
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Expires: 2017-09-18
Abstract
Abstract A reset signal is asserted to a processor. In response to the reset signal, the processor normally performs an instruction fetch cycle to a predetermined address. If the processor fails to perform the instruction fetch cycle or fails to perform the fetch cycle to the predetermined address within a predetermined period of time, an indication is provided that the processor reset has failed.
Inventors
- 👤 David I. Poisner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 10:03
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1415; G06F11/1441
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
114 words
A method for detecting and reporting that a reset of a processor has failed, the method comprising the steps of: issuing a reset signal to the processor; determining whether the processor fails to issue a first instruction fetch cycle within a predetermined period of time after the reset of the processor, the first instruction fetch cycle including a first instruction address; determining whether the first instruction address matches a predetermined address; indicating that the reset has failed if the first instruction fetch cycle is not issued from the processor within the predetermined period of time; and indicating that the reset has failed if the first instruction fetch address does not match the predetermined address.
Claim 2
Independent Claim
114 words
A method for detecting and reporting that a reset of a processor has failed, the method comprising the steps of: issuing a reset signal to the processor; determining whether the processor fails to issue a first instruction fetch cycle within a predetermined period of time after the reset of the processor, the first instruction fetch cycle including a first instruction address; determining whether the first instruction address matches a predetermined address; indicating that the reset has failed if the first instruction fetch cycle is not issued from the processor within the predetermined period of time; and indicating that the reset has failed if the first instruction fetch address does not match the predetermined address.
Claim 3
Dependent Claim
74 words
The method of claim 1 wherein the step of indicating that the reset has failed if the first instruction fetch cycle is not issued from the processor within the predetermined period of time further includes the steps of: starting a timer upon performing the step of issuing a reset signal to the processor; and indicating that the reset has failed if the timer expires before the first instruction fetch is issued from the processor.
Claim 4
Dependent Claim
59 words
The method of claim 1 wherein the step of indicating that the reset has failed if the first instruction fetch cycle is not issued from the processor within the predetermined period of time further includes the steps of: asserting an alert signal to a communications device; and transmitting information across a communications network indicating that the reset has failed.
Claim 5
Dependent Claim
47 words
The method of claim 1 wherein the step of indicating that the reset has failed if the first instruction fetch cycle is not issued from the processor within the predetermined period of time further includes the step of providing an aural indicator that the reset has failed.
Claim 6
Dependent Claim
47 words
The method of claim 1 wherein the step of indicating that the reset has failed if the first instruction fetch cycle is not issued from the processor within the predetermined period of time further includes the step of providing a visual indicator that the reset has failed.
Claim 7
Dependent Claim
22 words
The method of claim 5, wherein the step of providing a visual indicator includes the step causing a light-emitting diode to illuminate.
Claim 8
Dependent Claim
23 words
The method of claim 5, wherein the step of providing a visual indicator includes the step causing a light-emitting diode to blink periodically.
Claim 9
Independent Claim
56 words
A method for detecting and reporting that a reset of a processor has failed, the method comprising the steps of: issuing a reset signal to the processor; and indicating that the reset has failed if after a first instruction fetch cycle is issued from the processor the fetched first instruction does not match a predetermined instruction.
Claim 10
Independent Claim
56 words
A method for detecting and reporting that a reset of a processor has failed, the method comprising the steps of: issuing a reset signal to the processor; and indicating that the reset has failed if after a first instruction fetch cycle is issued from the processor the fetched first instruction does not match a predetermined instruction.
Claim 11
Dependent Claim
104 words
A computer system, comprising: a processor coupled to a bus; circuitry for performing a processor reset including circuitry for providing a reset signal to the processor, the reset signal causing the processor to fetch a first instruction from a predetermined address; circuitry for determining whether the processor fails to fetch the first instruction within a predetermined period of time; circuitry for determining whether the first instruction is fetched from an address that matches the predetermined address; and circuitry for indicating that the reset has failed if the processor fails to fetch the first instruction from the predetermined address within the predetermined period of time.
Claim 12
Dependent Claim
104 words
A computer system, comprising: a processor coupled to a bus; circuitry for performing a processor reset including circuitry for providing a reset signal to the processor, the reset signal causing the processor to fetch a first instruction from a predetermined address; circuitry for determining whether the processor fails to fetch the first instruction within a predetermined period of time; circuitry for determining whether the first instruction is fetched from an address that matches the predetermined address; and circuitry for indicating that the reset has failed if the processor fails to fetch the first instruction from the predetermined address within the predetermined period of time.
Claim 13
Dependent Claim
35 words
The computer system of claim 9 wherein the circuitry for indicating that the reset has failed includes a communications device that transmits information over a communications network, the information indicating that the reset has failed.
Claim 14
Dependent Claim
31 words
The computer system of claim 9 wherein the circuitry for indicating that the reset has failed includes a light emitting device that provides a visual indication that the reset has failed.
Claim 15
Dependent Claim
30 words
The computer system of claim 9 wherein the circuitry for indicating that the reset has failed includes an audio device that provides an aural indication that the reset has failed.
Claim 16
Dependent Claim
99 words
A semiconductor logic device, comprising: circuitry for performing a processor reset including circuitry for providing a reset signal to a processor, the reset signal causing the processor to fetch a first instruction from a predetermined address; circuitry for determining whether the processor fails to fetch the first instruction within a predetermined period of time; circuitry for determining whether the first instruction is fetched from an address that matches the predetermined address; and circuitry for indicating that the reset has failed if the processor fails to fetch the first instruction from the predetermined address within the predetermined period of time.
Claim 17
Dependent Claim
99 words
A semiconductor logic device, comprising: circuitry for performing a processor reset including circuitry for providing a reset signal to a processor, the reset signal causing the processor to fetch a first instruction from a predetermined address; circuitry for determining whether the processor fails to fetch the first instruction within a predetermined period of time; circuitry for determining whether the first instruction is fetched from an address that matches the predetermined address; and circuitry for indicating that the reset has failed if the processor fails to fetch the first instruction from the predetermined address within the predetermined period of time.
Claim 18
Dependent Claim
32 words
The semiconductor logic device of claim 13 wherein the circuitry for indicating that the reset has failed includes an alert signal that communicates to other system devices that the reset has failed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-10 | 2003-07-12 | 2004-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-10 | 2007-07-12 | 2008-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-10 | 2011-07-12 | 2012-01-11 | $7700.00 | Window Closed / Lapsed |