Patent US6013946A successfully refreshed from Google Patents.
US6013946A
Expired / Lapsed
US
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Wire bond packages for semiconductor chips and related methods and assemblies
Assignee: Samsung Electronics Co Ltd
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Filing: 1997-03-31
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Granted: 2000-01-11
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Expires: 2017-03-31
Abstract
Abstract A package for a semiconductor chip including a plurality of input/output pads includes an insulating layer and a plurality of conductive traces. The insulating layer has a first surface for bonding with the surface of the semiconductor chip so that the input/output pads are exposed adjacent the insulating layer. The conductive traces are provided on a second surface of the insulating layer opposite the first surface wherein each of the conductive traces corresponds to a respective one of the input/output pads. In particular, the conductive traces are adapted to receive a plurality of bonding wires each of which corresponds to a respective one of the input/output pads. Accordingly, each of the bonding wires can be bonded at a first end to the respective input/output pad and at a second end to the respective conductive trace. Furthermore, the input/output pads can be on an interior portion of the surface of the semiconductor chip, and the insulating layer can have an opening therein for exposing the input/output pads. Accordingly, a dam on the second surface of the insulating layer can be provided around the opening wherein each of the conductive traces extends from adjacent the opening under the dam to a portion of the insulating layer outside the dam. Related methods and assemblies are also discussed.
Inventors
- 👤 Kyu Jin Lee
- 👤 Do Soo Jeong
- 👤 Jae June Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 15:06
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W74/00; H10W74/10; H10W74/111; H10W74/129; H10W74/114; H10W74/117; H10W76/00; H10W76/40; H10W76/42; H10W76/47; H10W76/60; H10W90/00; H10W90/701; H10W90/751; H10W90/756; H10W95/00; H10W72/00; H10W72/01; H10W72/0198; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/851; H10W72/853; H10W72/865; H10W90/731; H10W90/734; H10W90/754
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
219 words
A semiconductor chip assembly comprising: a semiconductor chip including a plurality of input/output pads on a surface thereof wherein said input/output pads are on an interior portion of said surface of said semiconductor chip; an insulating layer on said surface of said semiconductor chip wherein said input/output pads are exposed adjacent said insulating layer wherein said insulating layer has an opening therein exposing said input/output pads; a plurality of conductive traces on said insulating layer opposite said semiconductor chip wherein each of said conductive traces corresponds to a respective one of said input/output pads; a plurality of bonding wires wherein each of said bonding wires corresponds to a respective one of said input/output pads and one of said conductive traces, and wherein each of said bonding wires is bonded at a first end to said respective input/output pad and at a second end to said respective conductive trace; a dam on said insulating layer opposite said semiconductor chip and around said opening wherein each of said conductive traces extends under said dam to a portion of said insulating layer outside said dam; a sealing lid on said dam wherein said sealing lid covers said opening, said bonding wires, and said input/output pads; at least one tie bar extending from said dam; and a rail connected to said tie bar.
Claim 2
Dependent Claim
219 words
A semiconductor chip assembly comprising: a semiconductor chip including a plurality of input/output pads on a surface thereof wherein said input/output pads are on an interior portion of said surface of said semiconductor chip; an insulating layer on said surface of said semiconductor chip wherein said input/output pads are exposed adjacent said insulating layer wherein said insulating layer has an opening therein exposing said input/output pads; a plurality of conductive traces on said insulating layer opposite said semiconductor chip wherein each of said conductive traces corresponds to a respective one of said input/output pads; a plurality of bonding wires wherein each of said bonding wires corresponds to a respective one of said input/output pads and one of said conductive traces, and wherein each of said bonding wires is bonded at a first end to said respective input/output pad and at a second end to said respective conductive trace; a dam on said insulating layer opposite said semiconductor chip and around said opening wherein each of said conductive traces extends under said dam to a portion of said insulating layer outside said dam; a sealing lid on said dam wherein said sealing lid covers said opening, said bonding wires, and said input/output pads; at least one tie bar extending from said dam; and a rail connected to said tie bar.
Claim 3
Dependent Claim
76 words
A semiconductor chip assembly according to claim 1 further comprising: a plurality of terminals on said insulating layer outside said dam wherein each of said terminals is electrically connected to a respective one of said conductive traces, wherein each of said terminals extends a first predetermined distance from said insulating layer, wherein said dam extends a second predetermined distance from said insulating layer, and wherein said first predetermined distance is greater than said second predetermined distance.
Claim 4
Dependent Claim
18 words
A semiconductor chip assembly according to claim 1 wherein said dam comprises a rectangular dam surrounding said opening.
Claim 5
Dependent Claim
29 words
A semiconductor chip assembly according to claim 1 wherein said dam, said at least one tie bar, and said rail are formed from a single layer of a material.
Claim 6
Dependent Claim
21 words
A semiconductor chip assembly according to claim 4 wherein said at least one tie bar includes a notch adjacent said dam.
Claim 7
Dependent Claim
197 words
A semiconductor chip assembly comprising: a semiconductor chip including a plurality of input/output pads on an interior portion of a surface thereof; an insulating layer on said surface of said semiconductor chip wherein said insulating layer has an opening therein exposing said input/output pads; a plurality of conductive traces on said insulating layer opposite said semiconductor chip wherein each of said conductive traces corresponds to a respective one of said input/output pads; a dam on said insulating layer opposite said semiconductor chip and around said opening wherein each of said conductive traces extends under said dam to a portion of said insulating layer outside said dam; a plurality of bonding wires wherein each of said bonding wires corresponds to a respective one of said input/output pads and one of said conductive traces, and wherein each of said bonding wires is bonded at a first end to said respective input/output pad and at a second end to said respective conductive trace; a sealing lid on said dam wherein said sealing lid covers said opening, said bonding wires, and said input/output pads; at least one tie bar extending from said dam; and a rail connected to said tie bar.
Claim 8
Dependent Claim
197 words
A semiconductor chip assembly comprising: a semiconductor chip including a plurality of input/output pads on an interior portion of a surface thereof; an insulating layer on said surface of said semiconductor chip wherein said insulating layer has an opening therein exposing said input/output pads; a plurality of conductive traces on said insulating layer opposite said semiconductor chip wherein each of said conductive traces corresponds to a respective one of said input/output pads; a dam on said insulating layer opposite said semiconductor chip and around said opening wherein each of said conductive traces extends under said dam to a portion of said insulating layer outside said dam; a plurality of bonding wires wherein each of said bonding wires corresponds to a respective one of said input/output pads and one of said conductive traces, and wherein each of said bonding wires is bonded at a first end to said respective input/output pad and at a second end to said respective conductive trace; a sealing lid on said dam wherein said sealing lid covers said opening, said bonding wires, and said input/output pads; at least one tie bar extending from said dam; and a rail connected to said tie bar.
Claim 9
Dependent Claim
76 words
A semiconductor chip assembly according to claim 6 further comprising: a plurality of terminals on said insulating layer outside said dam wherein each of said terminals is electrically connected to a respective one of said conductive traces, wherein each of said terminals extends a first predetermined distance from said insulating layer, wherein said dam extends a second predetermined distance from said insulating layer, and wherein said first predetermined distance is greater than said second predetermined distance.
Claim 10
Dependent Claim
18 words
A semiconductor chip assembly according to claim 6 wherein said dam comprises a rectangular dam surrounding said opening.
Claim 11
Dependent Claim
29 words
A semiconductor chip assembly according to claim 6 wherein said dam, said at least one tie bar, and said rail are formed from a single layer of a material.
Claim 12
Dependent Claim
21 words
A semiconductor chip assembly according to claim 9 wherein said at least one tie bar includes a notch adjacent said dam.
Claim 13
Dependent Claim
161 words
An intermediate package for a semiconductor chip including a plurality of input/output pads on an interior portion of a surface thereof, said intermediate package comprising: an insulating layer including a first surface for bonding with the surface of the semiconductor chip wherein said insulating layer has an opening therein for exposing the input/output pads; a plurality of conductive traces on a second surface of said insulating layer opposite said first surface wherein each of said conductive traces corresponds to a respective one of the input/output pads; a dam on said second surface of said insulating layer around said opening wherein each of said conductive traces extends from adjacent said opening under said dam to a portion of said insulating layer outside said dam; at least one tie bar extending from said dam; and a rail connected to said tie bar wherein said dam, said at least one tie bar, and said rail are formed from a single layer of a material.
Claim 14
Dependent Claim
161 words
An intermediate package for a semiconductor chip including a plurality of input/output pads on an interior portion of a surface thereof, said intermediate package comprising: an insulating layer including a first surface for bonding with the surface of the semiconductor chip wherein said insulating layer has an opening therein for exposing the input/output pads; a plurality of conductive traces on a second surface of said insulating layer opposite said first surface wherein each of said conductive traces corresponds to a respective one of the input/output pads; a dam on said second surface of said insulating layer around said opening wherein each of said conductive traces extends from adjacent said opening under said dam to a portion of said insulating layer outside said dam; at least one tie bar extending from said dam; and a rail connected to said tie bar wherein said dam, said at least one tie bar, and said rail are formed from a single layer of a material.
Claim 15
Dependent Claim
61 words
An intermediate package according to claim 11 wherein said conductive traces are adapted to receive a plurality of bonding wires each of which corresponds to a respective one of the input/output pads, so that each of said bonding wires can be bonded at a first end to the respective input/output pad and at a second end to said respective conductive trace.
Claim 16
Dependent Claim
75 words
An intermediate package according to claim 1 further comprising: a plurality of terminals on said insulating layer outside said dam wherein each of said terminals is electrically connected to a respective one of said conductive traces, wherein each of said terminals extends a first predetermined distance from said insulating layer, wherein said dam extends a second predetermined distance from said insulating layer, and wherein said first predetermined distance is greater than said second predetermined distance.
Claim 17
Dependent Claim
17 words
An intermediate package according to claim 11 wherein said dam comprises a rectangular dam surrounding said opening.
Claim 18
Dependent Claim
20 words
An intermediate package according to claim 11 wherein said at least one tie bar includes a notch adjacent said dam.
Claim 19
Dependent Claim
146 words
An intermediate semiconductor chip assembly comprising: a semiconductor chip including a plurality of input/output pads on an interior portion of a surface thereof; an insulating layer on said surface of said semiconductor chip wherein said insulating layer has an opening therein exposing said input/output pads; a plurality of conductive traces on said insulating layer opposite said semiconductor chip wherein each of said conductive traces corresponds to a respective one of said input/output pads; and a dam on said insulating layer opposite said semiconductor chip and around said opening wherein each of said conductive traces extends under said dam to a portion of said insulating layer outside said dam; at least one tie bar extending from said dam; and a rail connected to said tie bar wherein said dam, said at least one tie bar, and said rail are formed from a single layer of a material.
Claim 20
Dependent Claim
146 words
An intermediate semiconductor chip assembly comprising: a semiconductor chip including a plurality of input/output pads on an interior portion of a surface thereof; an insulating layer on said surface of said semiconductor chip wherein said insulating layer has an opening therein exposing said input/output pads; a plurality of conductive traces on said insulating layer opposite said semiconductor chip wherein each of said conductive traces corresponds to a respective one of said input/output pads; and a dam on said insulating layer opposite said semiconductor chip and around said opening wherein each of said conductive traces extends under said dam to a portion of said insulating layer outside said dam; at least one tie bar extending from said dam; and a rail connected to said tie bar wherein said dam, said at least one tie bar, and said rail are formed from a single layer of a material.
Claim 21
Dependent Claim
65 words
An intermediate semiconductor chip assembly according to claim 16 further comprising: a plurality of bonding wires wherein each of said bonding wires corresponds to a respective one of said input/output pads and one of said conductive traces, and wherein each of said bonding wires is bonded at a first end to said respective input/output pad and at a second end to said respective conductive trace.
Claim 22
Dependent Claim
31 words
An intermediate semiconductor chip assembly according to claim 17 further comprising: an encapsulant on said input/output pads, on said bonding wires, and on portions of said conductive traces inside said dam.
Claim 23
Dependent Claim
35 words
An intermediate semiconductor chip assembly according to claim 18 wherein said dam defines a window exposing said opening of said insulating layer and wherein said encapsulant is contained in said opening and in said window.
Claim 24
Dependent Claim
44 words
An intermediate semiconductor chip assembly according to claim 18 wherein said dam extends a first predetermined distance from said insulating layer, wherein said encapsulant extends a second predetermined distance from said insulating layer, and wherein said first distance is greater than said second distance.
Claim 25
Dependent Claim
16 words
An intermediate semiconductor chip assembly according to claim 18 wherein said encapsulant comprises a potting resin.
Claim 26
Dependent Claim
77 words
An intermediate semiconductor chip assembly according to claim 16 further comprising: a plurality of terminals on said insulating layer outside said dam wherein each of said terminals is electrically connected to a respective one of said conductive traces, wherein each of said terminals extends a first predetermined distance from said insulating layer, wherein said dam extends a second predetermined distance from said insulating layer, and wherein said first predetermined distance is greater than said second predetermined distance.
Claim 27
Dependent Claim
19 words
An intermediate semiconductor chip assembly according to claim 16 wherein said dam comprises a rectangular dam surrounding said opening.
Claim 28
Dependent Claim
31 words
An intermediate semiconductor chip assembly according to claim 17 further comprising: a sealing lid on said dam wherein said sealing lid covers said opening, said bonding wires, and said input/output pads.
Claim 29
Dependent Claim
22 words
An intermediate semiconductor chip assembly according to claim 16 wherein said at least one tie bar includes a notch adjacent said dam.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-10 | 2003-07-12 | 2004-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-10 | 2007-07-12 | 2008-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-10 | 2011-07-12 | 2012-01-11 | $7700.00 | Window Closed / Lapsed |