Semiconductor chip package

Claim 2

A semiconductor chip package, comprising: a. a semiconductor chip; b. conductive leads electrically connected to the chip, the conductive leads extending over an upper surface of the chip; c. encapsulating material covering at least a portion of the chip and at least a portion of the conductive leads, the encapsulating material having openings therein to expose electrode bond areas on the conductive leads; and d. electrodes contacting the electrode bond areas through the openings in the encapsulating material.

Claim 3

A semiconductor chip package according to claim 1, wherein the bond pads are electrically connected to active devices formed in the chip.

Claim 4

A semiconductor chip package according to claim 1, wherein the encapsulating material encapsulates the chip and the conductive leads extend out through the encapsulating material.

Claim 5

A semiconductor chip package according to claim 1, wherein the electrodes comprise a plurality of solder balls each approximating the size and shape of the openings in the encapsulating material, the solder balls being bonded to the leads through the openings in the encapsulating material.

Claim 6

A semiconductor chip package, comprising: a. a semiconductor chip; b. conductive leads electrically connected to the chip; c. encapsulating material encapsulating the chip and the conductive leads, the encapsuating material having openings therein to expose electrode bond areas on the conductive leads: and d. electrodes contacting the electrode bond areas through the openings in the encapsulating material.

Claim 7

A semiconductor chip package, comprising: a. a semiconductor chip; b. conductive leads electrically connected to the chip; c. encapsulating material encapsulating the chip and the conductive leads, the encapsuating material having openings therein to expose electrode bond areas on the conductive leads: and d. electrodes contacting the electrode bond areas through the openings in the encapsulating material.

Claim 8

A semiconductor chip package, comprising: a. a semiconductor chip having bond pads thereon, the bond pads being accessible from an upper surface of the chip; b. conductive leads extending over and attached to the upper surface of the chip; c. connecting means for electrically connecting the conductive leads to the bond pads; d. encapsulating material covering at least a portion of the upper surface of the chip, the bond pads, at least a portion of the conductive leads and the connecting means, the encapsulating material having openings therein to expose electrode bond areas on the conductive leads; and e. electrodes contacting the electrode bond areas through the openings in the encapsulating material.

Claim 9

A semiconductor chip package, comprising: a. a semiconductor chip having bond pads thereon, the bond pads being accessible from an upper surface of the chip; b. conductive leads extending over and attached to the upper surface of the chip; c. connecting means for electrically connecting the conductive leads to the bond pads; d. encapsulating material covering at least a portion of the upper surface of the chip, the bond pads, at least a portion of the conductive leads and the connecting means, the encapsulating material having openings therein to expose electrode bond areas on the conductive leads; and e. electrodes contacting the electrode bond areas through the openings in the encapsulating material.

Claim 10

A semiconductor chip package according to claim 6, wherein the bond pads are electrically connected to active devices formed in the chip.

Claim 11

A semiconductor chip package according to claim 6, wherein the bond pads are aligned along a central portion of the chip.

Claim 12

A semiconductor chip package according to claim 6, wherein the conductive leads are attached to the upper surface of the chip by a layer of adhesive material interposed between the conductive leads and the upper surface of the chip.

Claim 13

A semiconductor chip package according to claim 6, wherein the connecting means comprises a plurality of bond wires bonded to the conductive leads and the bond pads thereby electrically connecting the conductive leads to the bond pads.

Claim 14

A semiconductor chip package according to claim 6, wherein the encapsulating material is a thermosetting epoxy resin.

Claim 15

A semiconductor chip package according to claim 6, wherein the encapsulating material encapsulates the chip and the conductive leads extend out through the encapsulating material.

Claim 16

A semiconductor chip package according to claim 6, wherein the encapsulating material encapsulates the chip, the bond pads, the connection means and the conductive leads.

Claim 17

A semiconductor chip package, comprising: a. a semiconductor chip assembly comprising a semiconductor chip and discrete conductive leads at spaced apart locations above and adjacent to and in electrical contact with the chip, the semiconductor chip assembly being disposed within an encapsulating material; and b. electrode bumps extending through the encapsulating material to contact the conductive leads and protruding from the encapsulating material for connection to an external circuit.

Claim 18

A semiconductor chip package, comprising: a. a semiconductor chip assembly comprising a semiconductor chip and discrete conductive leads at spaced apart locations above and adjacent to and in electrical contact with the chip, the semiconductor chip assembly being disposed within an encapsulating material; and b. electrode bumps extending through the encapsulating material to contact the conductive leads and protruding from the encapsulating material for connection to an external circuit.

Claim 19

A semiconductor chip package according to claim 14, wherein the conductive leads have an outer end that extends out from the encapsulating material.

Claim 20

A semiconductor chip package, comprising: a. a semiconductor chip having active devices therein; b. a plurality of bond pads electrically connected to the active devices, the bond pads being aligned along a central portion of one surface of the chip; c. an insulating layer overlying the surface of the chip, the insulating layer having holes therein to enable electrical connection to the bond pads through the holes; d. a plurality of discrete conducting leads extending over and attached to the insulating layer, each lead having an inner end and an outer end, the inner end being located in close proximity to the bond pads; e. a plurality of bond wires bonded to wiring bond areas on the inner end of the leads and the bond pads on the chip thereby electrically connecting the leads to the bond pads; f. an encapsulating material disposed over and enclosing the chip, the bond pads, the inner end of the conducting leads and the bond wires, the encapsulating material having openings formed therein to expose electrode bond areas on the inner end of the conductive leads; and g. a plurality of solder balls each approximating the size and shape of the openings in the encapsulating material, the solder balls being bonded to the electrode bond areas through the openings in the encapsulating material.

Claim 21

A semiconductor chip package, comprising: a. a semiconductor chip having active devices therein; b. a plurality of bond pads electrically connected to the active devices, the bond pads being aligned along a central portion of one surface of the chip; c. an insulating layer overlying the surface of the chip, the insulating layer having holes therein to enable electrical connection to the bond pads through the holes; d. a plurality of discrete conducting leads extending over and attached to the insulating layer, each lead having an inner end and an outer end, the inner end being located in close proximity to the bond pads; e. a plurality of bond wires bonded to wiring bond areas on the inner end of the leads and the bond pads on the chip thereby electrically connecting the leads to the bond pads; f. an encapsulating material disposed over and enclosing the chip, the bond pads, the inner end of the conducting leads and the bond wires, the encapsulating material having openings formed therein to expose electrode bond areas on the inner end of the conductive leads; and g. a plurality of solder balls each approximating the size and shape of the openings in the encapsulating material, the solder balls being bonded to the electrode bond areas through the openings in the encapsulating material.

Claim 22

A semiconductor chip package according to claim 16, wherein the size and shape of the openings is defined by a desired size and shape of the solder balls after a reflow step.

Claim 23

A semiconductor chip package according to claim 16, wherein the conductive leads are severed substantially flush with the encapsulating material after encapsulation.