Patent US6009126A successfully refreshed from Google Patents.
US6009126A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Zero-IF receiver
Assignee: Hanger Solutions LLC
•
Filing: 1997-08-01
•
Granted: 1999-12-28
•
Expires: 2017-08-01
Abstract
Abstract Known is a zero intermediate frequency receiver or zero-IF receiver in which DC-offset correction is done in the I- and Q-paths, after mixing down of the received RF-signal or of an IF-signal. Such a DC-offset correction is not sufficient for high gain I- and Q-paths, particularly not in pagers for receiving long messages. Furthermore, no optimal power saving is achieved if such a receiver alternately operates in receive mode and sleep mode. A zero intermediate frequency receiver is proposed in which DC-offset correction is distributed over the high gain I- and Q-path. Preferably, blocking means are provided between DC-offset correction circuits and low pass filters in the I- and Q-path to prevent that an output signal of an upstream DC-offset correction circuit in the path excites a downstream low pass filter in the path during DC-offset correction. Herewith, considerable power savings are achieved.
Inventors
- 👤 Adrianus Van Bezooijen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:58
CPC Classifications
H; H03; H03D; H03D3/00; H03D3/007; H03D3/008; H04; H04B; H04B1/00; H04B1/06; H04B1/16; H04B1/30; H04L; H04L25/00; H04L25/02; H04L25/06; H03D2200/00; H03D2200/0041; H03D2200/0084
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
102 words
A zero intermediate frequency receiver comprising a local frequency generating arrangement which is coupled to a pair of quadrature related mixers for mixing down a received signal to a pair of quadrature related signals to be demodulated in an in-phase signal path and in a quadrature signal path, a path comprising a cascade of at least one low pass filter and at least two amplifiers, and a first DC-offset correction circuit between the amplifiers, characterized in that the path comprises at least a second DC-offset correction circuit which is distributed over the path for allowing the path to have a high gain.
Claim 2
Dependent Claim
102 words
A zero intermediate frequency receiver comprising a local frequency generating arrangement which is coupled to a pair of quadrature related mixers for mixing down a received signal to a pair of quadrature related signals to be demodulated in an in-phase signal path and in a quadrature signal path, a path comprising a cascade of at least one low pass filter and at least two amplifiers, and a first DC-offset correction circuit between the amplifiers, characterized in that the path comprises at least a second DC-offset correction circuit which is distributed over the path for allowing the path to have a high gain.
Claim 3
Dependent Claim
21 words
A zero intermediate frequency receiver according to claim 1, wherein the receiver is arranged to activate the DC-offset correction circuits sequentially.
Claim 4
Dependent Claim
34 words
A zero intermediate frequency receiver according to claim 1, wherein the second DC-offset correction circuit is coupled in the cascade before a first low pass filter of the at least one low pass filter.
Claim 5
Dependent Claim
50 words
A zero intermediate frequency receiver according to claim 3, wherein a second low pass filter of the at least one low pass filter is coupled to an output of the first DC-offset correction circuit, whereby the first low pass filter has a lower selectivity than the second low pass filter.
Claim 6
Dependent Claim
42 words
A zero intermediate frequency receiver according to claim 3, wherein the path comprises blocking means to prevent that an output signal of a upstream DC-offset correction circuit in the path excites an downstream low pass filter in the path during DC-offset correction.
Claim 7
Dependent Claim
32 words
A zero intermediate frequency receiver according to claim 5, wherein the blocking means comprises at least a first clamp circuit which is coupled to an input of the first low pass filter.
Claim 8
Dependent Claim
29 words
A zero intermediate frequency receiver according to claim 6, wherein the path comprises a first buffer amplifier for isolating the second DC-offset correction circuit from the first clamp circuit.
Claim 9
Dependent Claim
30 words
A zero intermediate frequency receiver according to claim 5, wherein the blocking means comprises a second clamp circuit which is coupled to an input of the second low pass filter.
Claim 10
Dependent Claim
29 words
A zero intermediate frequency receiver according to claim 8, wherein the path comprises a second buffer amplifier for isolating the first DC-offset correction circuit from the second clamp circuit.
Claim 11
Dependent Claim
48 words
A zero intermediate frequency receiver according to claim 1, wherein the receiver is arranged for operating in a power saving mode, whereby at least bias currents of at least the amplifiers, filters and DC-offset correction circuits are switched off if the receiver is in the power saving mode.
Claim 12
Dependent Claim
18 words
A zero intermediate frequency receiver according to claim 1, wherein the DC-offset correction circuits are droop-less sample-and-hold circuits.
Claim 13
Dependent Claim
59 words
A zero intermediate frequency receiver according to claim 11 wherein the droop-less sample-and-hold circuits are formed by a subtracter comprised in the path and a cascade of an analog-to-digital converter, a latch circuit, and a digital-to-analog converter coupled in a loop with the subtracter, an output of the digital-to-analog converter being coupled to a subtraction input of the subtracter.
Claim 14
Dependent Claim
30 words
A zero intermediate frequency receiver according to claim 12, wherein a low pass filter is provided between the output of the digital-to-analog converter and the subtraction input of the subtracter.
Claim 15
Dependent Claim
21 words
A zero intermediate frequency receiver according to claim 12, wherein the cascade is an analog-to-digital converter of the successive approximation type.
References Cited (Backward Citations)
US3953805A
Cited
US4736390A
Cited
US4944025A
Cited
EP0594894A1
Cited
US5422889A
Cited
US5438692A
Cited
US5584068A
Cited
US5724653A
Cited
US5953643A
Cited
US5896562A
Cited
US5918167A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-27 | 2003-06-28 | 2003-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-27 | 2007-06-28 | 2007-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-27 | 2011-06-28 | 2011-12-28 | $7700.00 | Window Closed / Lapsed |