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Patent US6009034A successfully refreshed from Google Patents.
US6009034A
Expired / Lapsed
US
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Memory device with distributed voltage regulation system
Assignee: Mosaid Technologies Inc
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Filing: 1998-10-05
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Granted: 1999-12-28
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Expires: 2018-10-05
Abstract
Abstract A memory device includes a memory cell array, control circuits, and a voltage regulation system. The voltage regulation system includes an array power bus distributing an array supply voltage to the array, and a control circuit power bus distributing a control circuit supply voltage to the control circuits. Regulator circuits are coupled to the array power bus at spaced-apart locations along the bus which allow each regulator circuit to respond independently to a localized variation in the array supply voltage. Other regulator circuits are similarly coupled to the control circuit power bus. The regulator circuits which are unneeded for a particular operating mode of the memory device can be turned off during active memory cycles, and all the regulator circuits can be turned off during stand-by memory cycles. A resistor couples the array and control circuit power busses, and a low-power regulator circuit is coupled to the control circuit power bus to maintain both the array and control circuit supply voltages during stand-by memory cycles while the regulator circuits are off. The voltage regulation system thus advantageously reduces the power consumption of the memory device by using the low-power regulator circuit alone during stand-by memory cycles, reduces noise from the array on the control circuit supply voltage by splitting the array and control circuit power busses, and provides more responsive regulation of the array and control circuit supply voltages by distributing the regulator circuits.
Inventors
- 👤 Troy A. Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:55
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/147
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
80 words
A memory device comprising: a memory cell array; and a voltage regulation system comprising: an array power bus operatively coupled to the memory cell array for distributing an array supply voltage to the memory cells of the array; and a regulator circuit operatively coupled to the array power bus at a plurality of respective spaced apart locations along the array power bus for regulating and providing the array supply voltage to the array power bus at respective spaced apart locations.
Claim 2
Dependent Claim
80 words
A memory device comprising: a memory cell array; and a voltage regulation system comprising: an array power bus operatively coupled to the memory cell array for distributing an array supply voltage to the memory cells of the array; and a regulator circuit operatively coupled to the array power bus at a plurality of respective spaced apart locations along the array power bus for regulating and providing the array supply voltage to the array power bus at respective spaced apart locations.
Claim 3
Dependent Claim
36 words
The memory device of claim 1 wherein the regulator circuit comprises a plurality of voltage regulators which are separately connected to the array power bus at a respective spaced apart locations along the array power bus.
Claim 4
Dependent Claim
16 words
The memory device of claim 1 wherein the memory device comprises a dynamic random access memory.
Claim 5
Dependent Claim
26 words
The memory device of claim 1 wherein the regulator circuit is constructed such that it can be turned off during stand-by cycles of the memory device.
Claim 6
Dependent Claim
38 words
The memory device of claim 4 wherein the voltage regulation system further comprises a low-power regulator circuit operatively coupled to the array power bus for providing a regulated array supply voltage while the other regulator circuit is off.
Claim 7
Dependent Claim
66 words
The memory device of claim 2, further comprising: a control circuit bus; and a plurality of control circuits each coupled to the control circuit bus and each having control outputs coupled to respective ones of the plurality of voltage regulators, the control circuits setting the control outputs to place the respective voltage regulators in a high power mode of operation or a normal mode of operation.
Claim 8
Dependent Claim
107 words
A computer system comprising: an input device; an output device; a processor operatively coupled to the input and output devices; and a memory device operatively coupled to the processor, the memory device comprising: a memory cell array; and a voltage regulation system comprising: an array power bus operatively coupled to the memory cell array for distributing an array supply voltage to the memory cell array; and a regulator circuit operatively coupled to the array power bus at a plurality of respective spaced apart locations along the array power bus for regulating and providing the array supply voltage to the array power bus at respective spaced apart locations.
Claim 9
Dependent Claim
107 words
A computer system comprising: an input device; an output device; a processor operatively coupled to the input and output devices; and a memory device operatively coupled to the processor, the memory device comprising: a memory cell array; and a voltage regulation system comprising: an array power bus operatively coupled to the memory cell array for distributing an array supply voltage to the memory cell array; and a regulator circuit operatively coupled to the array power bus at a plurality of respective spaced apart locations along the array power bus for regulating and providing the array supply voltage to the array power bus at respective spaced apart locations.
Claim 10
Dependent Claim
36 words
The computer system of claim 7 wherein the regulator circuit comprises a plurality of voltage regulators which are separately connected to the array power bus at a respective spaced apart locations along the array power bus.
Claim 11
Dependent Claim
16 words
The computer system of claim 7 wherein the memory device comprises a dynamic random access memory.
Claim 12
Dependent Claim
26 words
The computer system of claim 7 wherein the regulator circuit is constructed such that it can be turned off during stand-by cycles of the memory device.
Claim 13
Dependent Claim
45 words
The computer system of claim 10 wherein the voltage regulation system further comprises a low-power regulator circuit operatively coupled to the array power bus for providing a regulated array supply voltage during stand-by cycles of the memory device while the other regulator circuit is off.
Claim 14
Independent Claim
45 words
A method of operating a power supply circuit in a memory device comprising: coupling electrical power to one point on an array power bus during an initial period; and coupling electrical power to the array bus at multiple, spaced apart locations following the initial period.
Claim 15
Independent Claim
45 words
A method of operating a power supply circuit in a memory device comprising: coupling electrical power to one point on an array power bus during an initial period; and coupling electrical power to the array bus at multiple, spaced apart locations following the initial period.
Claim 16
Dependent Claim
22 words
The method of claim 12, further comprising coupling electrical power from the array bus to the array at multiple, spaced apart locations.
Claim 17
Dependent Claim
22 words
The method of claim 12, further comprising discontinuing coupling electrical power to the array bus during stand-by cycles of the memory device.
Claim 18
Dependent Claim
46 words
The method of claim 14, further comprising: comparing a voltage on the array power bus to a first reference voltage; and coupling the array power bus to an external supply voltage when the voltage on the array power bus is less than the first reference voltage.
Claim 19
Dependent Claim
39 words
The method of claim 12, further comprising: discontinuing coupling electrical power to the array bus during stand-by cycles of the memory device; and supplying a low voltage power supply voltage to the array power bus during the stand-by cycles.
Claim 20
Dependent Claim
38 words
The method of claim 12 wherein coupling electrical power to one point on the array bus comprises coupling an external supply voltage for a period of time at the beginning of an active cycle of the memory device.
Claim 21
Dependent Claim
70 words
The method of claim 12 wherein coupling electrical power to the array bus at multiple, spaced apart locations comprises: coupling a first enabling signal to a first regulator circuit having a first regulated output terminal coupled to a first point on the array bus; and coupling a second enabling signal to a second regulator circuit having a second regulated output terminal coupled to a second point on the array bus.
Claim 22
Dependent Claim
48 words
The method of claim 12 wherein coupling electrical power to the array bus at multiple, spaced apart locations comprises coupling a plurality of enabling signals to a respective plurality of regulator circuits each having a respective regulated output terminal coupled to a respective location of the array bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-27 | 2003-06-28 | 2003-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-27 | 2007-06-28 | 2007-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-27 | 2011-06-28 | 2011-12-28 | $7700.00 | Window Closed / Lapsed |