US6008534A
Expired / Lapsed
US
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Integrated circuit package having signal traces interposed between power and ground conductors in order to form stripline transmission lines
Assignee: Adeia Semiconductor Technologies LLC
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Filing: 1998-01-14
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Granted: 1999-12-28
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Expires: 2018-01-14
Abstract
Abstract A semiconductor device package is presented having signal traces interposed between power and ground conductors in order to form stripline transmission lines. The semiconductor device package includes a substrate having a die area defined upon an upper surface. The die area is dimensioned to receive the integrated circuit. A first planar conductive layer formed upon the upper surface includes a first set of bonding pads and a set of conductive traces. Members of the first set of bonding pads are arranged upon the upper surface proximate the die area, and are used to make electrical connections to the integrated circuit. Members of the set of conductive traces are connected between one of two polarities of a power supply and corresponding members of the first set of bonding pads, and function as reference planes for underlying signal traces. A second planar conductive layer is positioned between the first planar conductive layer and an underside surface of the substrate. The second conductive layer is connected to the other of the two polarities of the power supply, and also functions as a reference plane for signal traces within the substrate. A planar conductive signal layer is interposed between the first and second conductive layers and patterned to form a set of signal traces. The signal traces form stripline transmission lines which are highly desirable in high frequency applications as their impedances are highly predictable and controllable.
Inventors
- 👤 Edwin M. Fulcher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:11
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/20; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/685; H05; H05K; H05K1/00; H05K1/02; H05K1/0213; H05K1/0237; H05K1/025; H05K1/0296; H05K1/0298; H05K2201/00; H05K2201/10; H05K2201/10613; H05K2201/10621; H05K2201/10734; H10W44/203; H10W44/209; H10W70/62; H10W70/65; H10W70/654; H10W70/655; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W74/00; H10W74/10; H10W74/15; H10W90/00; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/734
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
186 words
A semiconductor device package for housing an integrated circuit and having a substrate comprising: a die area defined upon an upper surface of the substrate and dimensioned to receive the integrated circuit; a first planar conductive layer formed upon the upper surface, comprising: a first set of bonding pads arranged upon the upper surface proximate the die area for making electrical connections to the integrated circuit; and a set of conductive traces connected between one of at least two polarities of a source of electrical power and corresponding members of the first set of bonding pads; a second planar conductive layer positioned between the first planar conductive layer and an underside surface of the substrate, wherein the second conductive layer is connected to another of said at least two polarities of the source of electrical power; and a planar conductive signal layer interposed between the first and second conductive layers and comprising a set of signal traces, wherein the signal traces are positioned between the conductive traces of the first conductive layer and the second conductive layer such that the signal traces form stripline transmission lines.
Claim 2
Dependent Claim
186 words
A semiconductor device package for housing an integrated circuit and having a substrate comprising: a die area defined upon an upper surface of the substrate and dimensioned to receive the integrated circuit; a first planar conductive layer formed upon the upper surface, comprising: a first set of bonding pads arranged upon the upper surface proximate the die area for making electrical connections to the integrated circuit; and a set of conductive traces connected between one of at least two polarities of a source of electrical power and corresponding members of the first set of bonding pads; a second planar conductive layer positioned between the first planar conductive layer and an underside surface of the substrate, wherein the second conductive layer is connected to another of said at least two polarities of the source of electrical power; and a planar conductive signal layer interposed between the first and second conductive layers and comprising a set of signal traces, wherein the signal traces are positioned between the conductive traces of the first conductive layer and the second conductive layer such that the signal traces form stripline transmission lines.
Claim 3
Dependent Claim
43 words
The semiconductor device package as recited in claim 1, further comprising a second set of bonding pads arranged upon the underside surface of the substrate, wherein members of the second set of bonding pads function as device terminals of the semiconductor device package.
Claim 4
Dependent Claim
32 words
The semiconductor device package as recited in claim 1, wherein members of the first set of bonding pads are arranged within the die area for C4 electrical connection to the integrated circuit.
Claim 5
Dependent Claim
33 words
The semiconductor device package as recited in claim 1, wherein members of the first set of bonding pads are arranged about the die area for wire bonding electrical connection to the integrated circuit.
Claim 6
Dependent Claim
24 words
The semiconductor device package as recited in claim 1, wherein the signal layer is isolated from the first conductive layer by a dielectric layer.
Claim 7
Dependent Claim
24 words
The semiconductor device package as recited in claim 1, wherein the signal layer is isolated from the second conductive layer by a dielectric layer.
Claim 8
Dependent Claim
35 words
The semiconductor device package as recited in claim 1, wherein the second conductive layer comprises a plurality of laterally spaced conductors adapted to receive said at least two polarities of the source of electrical power.
Claim 9
Dependent Claim
16 words
The semiconductor device package as recited in claim 1, wherein the substrate comprises an epoxy material.
Claim 10
Dependent Claim
16 words
The semiconductor device package as recited in claim 1, wherein the substrate comprises a ceramic material.
Claim 11
Dependent Claim
16 words
The semiconductor device package as recited in claim 1, wherein the substrate comprises a polyimide material.
Claim 12
Dependent Claim
22 words
The semiconductor device package as recited in claim 2, wherein members of the second set of bonding pads are coated with solder.
Claim 13
Dependent Claim
60 words
The semiconductor device package as recited in claim 2, further comprising a set of vias connecting members of the first set of bonding pads to corresponding signal traces and the signal traces to corresponding members of the second set of bonding pads such that signal paths are formed between corresponding members of the first and second sets of bonding pads.
Claim 14
Dependent Claim
222 words
An assembly, comprising: an integrated circuit having a plurality of input/output (I/O) pads arranged upon a surface; a substrate having opposed planar upper and underside surfaces, wherein the substrate comprises: a die area defined upon the upper surface and dimensioned to receive the integrated circuit; a first planar conductive layer formed upon the upper surface, comprising: a first set of bonding pads arranged upon the upper surface proximate the die area for making electrical connections to the integrated circuit; and a set of conductive traces connected between one of at least two polarities of a source of electrical power and corresponding members of the first set of bonding pads; a second planar conductive layer positioned between the first planar conductive layer and an underside surface of the substrate, wherein the second conductive layer is connected to another of said at least two polarities of the source of electrical power; and a planar conductive signal layer interposed between the first and second conductive layers and comprising a set of signal traces, wherein the signal traces are positioned between the conductive traces of the first conductive layer and the second conductive layer such that the signal traces form stripline transmission lines; and wherein the plurality I/O pads of the integrated circuit are electrically connected to corresponding members of the first set of bonding pads.
Claim 15
Dependent Claim
222 words
An assembly, comprising: an integrated circuit having a plurality of input/output (I/O) pads arranged upon a surface; a substrate having opposed planar upper and underside surfaces, wherein the substrate comprises: a die area defined upon the upper surface and dimensioned to receive the integrated circuit; a first planar conductive layer formed upon the upper surface, comprising: a first set of bonding pads arranged upon the upper surface proximate the die area for making electrical connections to the integrated circuit; and a set of conductive traces connected between one of at least two polarities of a source of electrical power and corresponding members of the first set of bonding pads; a second planar conductive layer positioned between the first planar conductive layer and an underside surface of the substrate, wherein the second conductive layer is connected to another of said at least two polarities of the source of electrical power; and a planar conductive signal layer interposed between the first and second conductive layers and comprising a set of signal traces, wherein the signal traces are positioned between the conductive traces of the first conductive layer and the second conductive layer such that the signal traces form stripline transmission lines; and wherein the plurality I/O pads of the integrated circuit are electrically connected to corresponding members of the first set of bonding pads.
Claim 16
Dependent Claim
23 words
The assembly as recited in claim 13, wherein the integrated circuit comprises at least one electronic device formed upon a monolithic semiconductor substrate.
Claim 17
Dependent Claim
41 words
The assembly as recited in claim 13, further comprising a second set of bonding pads arranged upon the underside surface of the substrate, wherein members of the second set of bonding pads function as device terminals of the semiconductor device package.
Claim 18
Dependent Claim
37 words
The assembly as recited in claim 13, wherein members of the first set of bonding pads are arranged within the die area and aligned with corresponding members of the plurality of I/O pads of the integrated circuit.
Claim 19
Dependent Claim
29 words
The assembly as recited in claim 13, wherein members of the plurality of I/O pads and corresponding bonding pads are connected to retain said integrated circuit upon the substrate.
Claim 20
Dependent Claim
41 words
The assembly as recited in claim 13, wherein members of the first set of bonding pads are arranged about the die area and electrically connected to corresponding members of the plurality of I/O pads of the integrated circuit by bonding wires.
Claim 21
Dependent Claim
33 words
The assembly as recited in claim 13, wherein the second conductive layer comprises a plurality of laterally spaced conductors adapted to receive said at least two polarities of the source of electrical power.
Claim 22
Dependent Claim
14 words
The assembly as recited in claim 13, wherein the substrate comprises an epoxy material.
Claim 23
Dependent Claim
14 words
The assembly as recited in claim 13, wherein the substrate comprises a ceramic material.
Claim 24
Dependent Claim
14 words
The assembly as recited in claim 13, wherein the substrate comprises a polyimide material.
Claim 25
Dependent Claim
20 words
The assembly as recited in claim 15, wherein members of the second set of bonding pads are coated with solder.
Claim 26
Dependent Claim
58 words
The assembly as recited in claim 15, further comprising a set of vias connecting members of the first set of bonding pads to corresponding signal traces and the signal traces to corresponding members of the second set of bonding pads such that signal paths are formed between corresponding members of the first and second sets of bonding pads.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-27 | 2003-06-28 | 2003-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-27 | 2007-06-28 | 2007-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-27 | 2011-06-28 | 2011-12-28 | $7700.00 | Window Closed / Lapsed |