Abstract Disclosed a conrol method and an apparatus for performing high speed burst operation in memory device which can perform high speed burst read/write operations at a speed superior to be superior to an operation speed of a burst EDO mode type DRAM by shortening a CAS access time tCAC, and can produce an identical package using signals which are used in a memory device of a EDO mode type DRAM. The method comprising the steps of preparing an "Idle" status where an internal circuit is precharged after a "Power On" status, determining a read mode, a write mode, a read/write mode, or a write/read mode in accordance with a /WE signal at a falling edge of a /CAS signal in which a column address is inputted in a case of a "Row Open" status by an instruction which is inputted during the "Idle" status, and automatically returning to the "Row Open" status if an operation of the read, write, read/write, or write/read mode is ended. Accordingly, the present invention can be used for a 66 MHz bus clock frequency which can not be applied to the conventional burst EDO mode type DRAM, and for the next generation 75-100 MHz bus clocks frequency. Further, there is an advantage that the present invention does not use the external clock, unlike a synchronous type DRAM, thereby reducing the power consumption of the total memory system.
An apparatus for performing high speed burst operation in memory device, the apparatus comprising: a CAS clock generator for outputting a CAS clock with same phase in accordance with a CAS signal which is inputted therein; a column address latch circuit for being synchronized by a CAS clock and latching an output signal of a column address buffer; a burst address counter for being synchronized by the CAS clock and outputting a column address signal to the column address latch circuit; a column decoder for being synchronized by the CAS clock and selecting data for the corresponding cells by receiving the column address signal stored in the column address latch circuit; and a data-out buffer for being synchronized by the CAS clock wherein control signals /WE and /OE of the memory device are clock pulse type signals in an active mode and are controlled by the CAS clock.
Claim 2
Independent Claim
148 words
An apparatus for performing high speed burst operation in memory device, the apparatus comprising: a CAS clock generator for outputting a CAS clock with same phase in accordance with a CAS signal which is inputted therein; a column address latch circuit for being synchronized by a CAS clock and latching an output signal of a column address buffer; a burst address counter for being synchronized by the CAS clock and outputting a column address signal to the column address latch circuit; a column decoder for being synchronized by the CAS clock and selecting data for the corresponding cells by receiving the column address signal stored in the column address latch circuit; and a data-out buffer for being synchronized by the CAS clock wherein control signals /WE and /OE of the memory device are clock pulse type signals in an active mode and are controlled by the CAS clock.
Claim 3
Dependent Claim
31 words
The apparatus as set forth in claim 1, further comprising a sense amplifier & input/output gate circuit which is synchronized by the CAS clock to inputs/outputs the data to/from cell array.
Claim 4
Dependent Claim
115 words
A control method for performing high speed burst operation in a memory device, the method comprising the steps of: a) receiving a /CAS signal; b) generating an internal clock signal in response to the /CAS signal; c) synchronizing a column path operation of the memory device with the internal clock signal; d) generating a control signal /WE with a first clock pulse type signal in an active mode including a write operation mode and a read operation mode; and e) generating a control signal /OE with a second clock pulse type signal in the read operation mode; wherein the first and second clock pulse type signals are controlled and activated by the internal clock signal.
Claim 5
Dependent Claim
115 words
A control method for performing high speed burst operation in a memory device, the method comprising the steps of: a) receiving a /CAS signal; b) generating an internal clock signal in response to the /CAS signal; c) synchronizing a column path operation of the memory device with the internal clock signal; d) generating a control signal /WE with a first clock pulse type signal in an active mode including a write operation mode and a read operation mode; and e) generating a control signal /OE with a second clock pulse type signal in the read operation mode; wherein the first and second clock pulse type signals are controlled and activated by the internal clock signal.