Patent US6004864A successfully refreshed from Google Patents.
US6004864A
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Ion implant method for forming trench isolation for integrated circuit devices
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1998-02-25
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Granted: 1999-12-21
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Expires: 2018-02-25
Abstract
Abstract A method is described for forming trench isolation for integrated circuits on silicon wafers by selectively doping the trench regions by ion implantation and then etching these areas with a wet chemical etch. A dopant such as boron, is implanted in a sequence of energies and doses to provide a desired trench profile of heavily doped silicon. The implanted silicon etches far more rapidly than the surrounding silicon and is readily etched out forming a trench. The concentration of dopant diminishes rapidly in the periphery of the implanted region. As the etch front approaches the periphery, the silicon etch rate, likewise diminishes and the etch can be quenched to leave a uniform surface layer of enhanced boron concentration which lines the resultant trench to form an effective channel stop. Wet etched trenches provide advantages over trenches formed by RIE including smooth rounded trench profiles which reduce stress. In addition, trenches having widths below 0.25 microns and essentially vertical walls can readily be formed.
Inventors
- 👤 Ji-Chung Huang
- 👤 Han-Liang Tseng
- 👤 Chia-Hsiang Chen
- 👤 Kuo-Sheng Chuang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:05
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0148; H10W10/031; H10W10/10; H10W10/17; H10W10/30; Y; Y10; Y10S; Y10S148/00; Y10S148/05
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
69 words
A method for forming a trench in a silicon wafer comprising: (a) providing a silicon wafer; (b) forming a mask defining a trench over said silicon wafer; (c) implanting said silicon wafer with ions in a plurality of ion implantation steps thereby forming an implanted region having a trench profile; (d) annealing said silicon wafer; and (e) etching said implanted region with a wet etch thereby forming a trench.
Claim 2
Independent Claim
69 words
A method for forming a trench in a silicon wafer comprising: (a) providing a silicon wafer; (b) forming a mask defining a trench over said silicon wafer; (c) implanting said silicon wafer with ions in a plurality of ion implantation steps thereby forming an implanted region having a trench profile; (d) annealing said silicon wafer; and (e) etching said implanted region with a wet etch thereby forming a trench.
Claim 3
Dependent Claim
14 words
The method of claim 1 wherein said mask comprises silicon nitride over silicon oxide.
Claim 4
Dependent Claim
20 words
The method of claim 1 wherein said ions are selected from the group consisting of boron, arsenic, phosphorous, and antimony.
Claim 5
Dependent Claim
25 words
The method of claim 1 wherein said etchant is a composition containing components selected from the group consisting of HF, HNO 3 , and KOH.
Claim 6
Dependent Claim
24 words
The method of claim 1 wherein said ions are boron and said annealing is rapid thermal annealing at a temperature greater than 850° C.
Claim 7
Dependent Claim
16 words
The method of claim 1 wherein said trench has a width of less than 0.25 microns.
Claim 8
Independent Claim
110 words
A method for forming trench isolation on a p-type silicon wafer comprising: (a) providing a p-type silicon wafer; (b) forming a mask defining a trench over said silicon wafer; (c) implanting said silicon wafer with boron in a plurality of ion implantation steps thereby forming an implanted region having a trench profile; (d) annealing said silicon wafer; (e) partially etching said implanted region with a wet etch thereby forming a trench while retaining a peripheral portion of said implanted region, said peripheral portion forming a continuous lining of enhanced boron concentration in said trench comprising a channel stop; and (f) filling said trench with a material thereby forming trench isolation.
Claim 9
Independent Claim
110 words
A method for forming trench isolation on a p-type silicon wafer comprising: (a) providing a p-type silicon wafer; (b) forming a mask defining a trench over said silicon wafer; (c) implanting said silicon wafer with boron in a plurality of ion implantation steps thereby forming an implanted region having a trench profile; (d) annealing said silicon wafer; (e) partially etching said implanted region with a wet etch thereby forming a trench while retaining a peripheral portion of said implanted region, said peripheral portion forming a continuous lining of enhanced boron concentration in said trench comprising a channel stop; and (f) filling said trench with a material thereby forming trench isolation.
Claim 10
Dependent Claim
14 words
The method of claim 7 wherein said mask comprises silicon nitride over silicon oxide.
Claim 11
Dependent Claim
25 words
The method of claim 7 wherein said etchant is a composition containing components selected from the group consisting of HF, HNO 3 , and KOH.
Claim 12
Dependent Claim
19 words
The method of claim 7 wherein said annealing is rapid thermal annealing at a temperature greater than 850° C.
Claim 13
Dependent Claim
11 words
The method of claim 7 wherein said material is silicon oxide.
Claim 14
Dependent Claim
13 words
The method of claim 7 wherein said material comprises polysilicon over silicon oxide.
Claim 15
Dependent Claim
16 words
The method of claim 7 wherein said trench has a width of less than 0.25 microns.
Claim 16
Independent Claim
98 words
A method for forming integrated circuit devices on a silicon wafer having trench isolation comprising: (a) providing a silicon wafer; (b) forming a mask defining a trench over said silicon wafer; (c) implanting said silicon wafer with boron ions in a plurality of ion implantation steps thereby forming an implanted region having a trench profile; (d) annealing said silicon wafer; (e) etching said implanted region with a wet etch thereby forming a trench; (f) filling said trench with a material thereby forming trench isolation; and (g) forming semiconductive devices on said silicon wafer adjacent to said trench isolation.
Claim 17
Independent Claim
98 words
A method for forming integrated circuit devices on a silicon wafer having trench isolation comprising: (a) providing a silicon wafer; (b) forming a mask defining a trench over said silicon wafer; (c) implanting said silicon wafer with boron ions in a plurality of ion implantation steps thereby forming an implanted region having a trench profile; (d) annealing said silicon wafer; (e) etching said implanted region with a wet etch thereby forming a trench; (f) filling said trench with a material thereby forming trench isolation; and (g) forming semiconductive devices on said silicon wafer adjacent to said trench isolation.
Claim 18
Dependent Claim
14 words
The method of claim 14 wherein said mask comprises silicon nitride over silicon oxide.
Claim 19
Dependent Claim
25 words
The method of claim 14 wherein said etchant is a composition containing components selected from the group consisting of HF, HNO 3 , and KOH.
Claim 20
Dependent Claim
19 words
The method of claim 14 wherein said annealing is rapid thermal annealing at a temperature greater than 850° C.
Claim 21
Dependent Claim
12 words
The method of claim 14 wherein said semiconductive devices are n-channel MOSFETs.
Claim 22
Dependent Claim
37 words
The method of claim 18 wherein said etching of said implanted region is quenched to retain a peripheral portion of said implanted region, which forms a continuous lining with enhanced boron concentration thereby providing a channel stop.
Claim 23
Dependent Claim
11 words
The method of claim 14 wherein said material is silicon oxide.
Claim 24
Dependent Claim
13 words
The method of claim 14 wherein said material comprises polysilicon over silicon oxide.
Claim 25
Dependent Claim
16 words
The method of claim 14 wherein said trench has a width of less than 0.25 microns.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-20 | 2003-06-21 | 2003-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-20 | 2007-06-21 | 2007-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-20 | 2011-06-21 | 2011-12-21 | $7700.00 | Window Closed / Lapsed |