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US6004862A
Expired / Lapsed
US
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Core array and periphery isolation technique
Assignee: GlobalFoundries Inc
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Filing: 1998-01-20
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Granted: 1999-12-21
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Expires: 2018-01-20
Abstract
Abstract A process for forming a semiconductor integrated circuit with a core area densely populated with active devices and with a periphery area less densely populated with active devices as compared to the core area, comprising the steps of: forming a first layer of first insulator material above a semiconductor substrate having a core area and a periphery area, wherein the first insulator material constitutes a polish stop for polishing processes and also as an oxidation barrier; patterning the first layer of first insulator material to expose first portions of the semiconductor substrate substantially only in the core area while using the first insulator material to substantially mask the periphery area; forming a plurality of trenches into the exposed first portions of semiconductor substrate in the core area; filling the plurality of trenches with an insulator; polishing down to the first layer of first insulator material; removing the first layer of first insulator material; forming a second layer of first insulator material over the core and periphery areas; forming openings down into the second layer of first insulator material to expose second portions of the semiconductor substrate substantially only in the periphery area while using the second layer to substantially mask the core area; and forming an isolation region in the exposed second portions of the semiconductor substrate.
Inventors
- 👤 Unsoon Kim
- 👤 Hung-Sheng Chen
- 👤 Kashmir Sahota
- 👤 Yu Sun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:40
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/014; H10W10/10; H10W10/13; H10W10/17
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
216 words
A process for forming a semiconductor integrated circuit with a core area densely populated with active devices and with a periphery area less densely populated with active devices as compared to said core area, comprising the steps of: forming a first layer of first insulator material above a semiconductor substrate having a core area and a periphery area, wherein said first insulator material constitutes a polish stop for polishing processes and also an oxidation barrier; patterning said first layer of first insulator material to expose first portions of said semiconductor substrate substantially only in said core area while using said first insulator material to substantially mask said periphery area; forming a plurality of trenches into said exposed first portions of semiconductor substrate in said core area; filling said plurality of trenches with an insulator; polishing down to said first layer of first insulator material; removing said first layer of first insulator material; forming a second layer of first insulator material over said core and periphery areas; forming openings down into said second layer of first insulator material to expose second portions of said semiconductor substrate substantially only in said periphery area while using said second layer to substantially mask said core area; and forming an isolation region in said exposed second portions of said semiconductor substrate.
Claim 2
Dependent Claim
216 words
A process for forming a semiconductor integrated circuit with a core area densely populated with active devices and with a periphery area less densely populated with active devices as compared to said core area, comprising the steps of: forming a first layer of first insulator material above a semiconductor substrate having a core area and a periphery area, wherein said first insulator material constitutes a polish stop for polishing processes and also an oxidation barrier; patterning said first layer of first insulator material to expose first portions of said semiconductor substrate substantially only in said core area while using said first insulator material to substantially mask said periphery area; forming a plurality of trenches into said exposed first portions of semiconductor substrate in said core area; filling said plurality of trenches with an insulator; polishing down to said first layer of first insulator material; removing said first layer of first insulator material; forming a second layer of first insulator material over said core and periphery areas; forming openings down into said second layer of first insulator material to expose second portions of said semiconductor substrate substantially only in said periphery area while using said second layer to substantially mask said core area; and forming an isolation region in said exposed second portions of said semiconductor substrate.
Claim 3
Dependent Claim
59 words
A process as defined in claim 1, wherein said first layer forming step comprises the step of forming said first layer of first insulator material above a semiconductor substrate that has a tunnel oxide layer directly over said semiconductor substrate, a layer of doped polysilicon over said tunnel oxide, and a high temperature oxide layer over said polysilicon layer.
Claim 4
Dependent Claim
26 words
A process as defined in claim 1, wherein said trench forming step comprises the step of anisotropically etching said exposed first portions of said semiconductor substrate.
Claim 5
Dependent Claim
19 words
A process as defined in claim 1, wherein said polishing step comprises the step of chemical-mechanical polishing said semiconductor.
Claim 6
Dependent Claim
37 words
A process as defined in claim 1, wherein said first layer forming step comprises the step of forming said first layer of first insulator material over an oxide layer which is formed directly over said semiconductor substrate.
Claim 7
Dependent Claim
30 words
A process as defined in claim 1, wherein said isolation region forming step comprises the step of forming a field oxide in said exposed second portions of said semiconductor substrate.
Claim 8
Dependent Claim
15 words
A process as defined in claim 1, wherein said first insulator material is silicon nitride.
Claim 9
Dependent Claim
194 words
A process for forming a semiconductor integrated circuit with a core area densely populated with active devices and with a periphery area less densely populated with active devices as compared to said core area, comprising the steps of: forming a first layer of silicon nitride above a semiconductor substrate having a core area and a periphery area; patterning said first layer of silicon nitride to expose first portions of said semiconductor substrate substantially only in said core area while using said silicon nitride to substantially mask said periphery area; forming a plurality of trenches into said exposed first portions of said semiconductor substrate in said core area; filling said plurality of trenches with an insulator; polishing down to said first layer of silicon nitride; removing said first silicon nitride layer; forming a second layer of silicon nitride over said core and periphery areas; forming openings down into said second layer of silicon nitride to expose second portions of said semiconductor substrate substantially only in said periphery area while using said second silicon nitride layer to substantially mask said core area; and forming an isolation region in said exposed second portions of said semiconductor substrate.
Claim 10
Dependent Claim
194 words
A process for forming a semiconductor integrated circuit with a core area densely populated with active devices and with a periphery area less densely populated with active devices as compared to said core area, comprising the steps of: forming a first layer of silicon nitride above a semiconductor substrate having a core area and a periphery area; patterning said first layer of silicon nitride to expose first portions of said semiconductor substrate substantially only in said core area while using said silicon nitride to substantially mask said periphery area; forming a plurality of trenches into said exposed first portions of said semiconductor substrate in said core area; filling said plurality of trenches with an insulator; polishing down to said first layer of silicon nitride; removing said first silicon nitride layer; forming a second layer of silicon nitride over said core and periphery areas; forming openings down into said second layer of silicon nitride to expose second portions of said semiconductor substrate substantially only in said periphery area while using said second silicon nitride layer to substantially mask said core area; and forming an isolation region in said exposed second portions of said semiconductor substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-20 | 2003-06-21 | 2003-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-20 | 2007-06-21 | 2007-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-20 | 2011-06-21 | 2011-12-21 | $7700.00 | Window Closed / Lapsed |