Patent US5994194A successfully refreshed from Google Patents.
US5994194A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-aligned base ohmic metal for an HBT device cross-reference to related applications
Assignee: Northrop Grumman Systems Corp
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Filing: 1998-05-07
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Granted: 1999-11-30
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Expires: 2018-05-07
Abstract
Abstract A relatively simple method for providing relatively close spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) on a relatively uniform basis. An emitter and base layer are epitaxially grown on a substrate. An emitter mesa is patterned with an i-line negative photoresist using conventional photolithography. Baking before and after exposure is used to form a resist pattern with a re-entrant profile having about a 0.1 μm resist overhang. The emitter layer is then etched with a wet etch and or isotropic dry etch to expose a portion of the base ohmic metal to make contact with the base. A second layer of an i-line negative photoresist is applied over the first photoresist. The second layer is used to pattern the base ohmic metal mask. The base ohmic metal is deposited by evaporation. The resist is stripped from the emitter mesa and the non-base ohmic metal regions which lifts the metal deposited on the resist leaving the metal in the base ohmic metal regions, aligned to the emitter mesa at a uniform spacing.
Inventors
- 👤 Michael D. Lammert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:15
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; H10P; H10P10/00; Y; Y10; Y10S; Y10S148/00; Y10S148/072; Y10S148/10; Y10S438/00; Y10S438/926; Y10S438/942; Y10S438/944; Y10S438/945; Y10S438/948; Y10S438/951
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
186 words
A method for controlling the spacing between an ohmic metal and an emitter mesa on an integrated circuit formed with a substrate and a plurality of vertically stacked epitaxial layers, including a base layer and an emitter layer formed on top, the method comprising the steps of: (a) depositing an emitter mesa photoresist on top of said emitter layer; (b) forming said emitter mesa photoresist to have a re-entrant profile, defining an overhand on top of said emitter mesa; (c) etching said emitter layer to form an emitter mesa and exposing said base layer, said emitter mesa photoresist overhanging said emitter mesa with said re-entrant profile after said etching; (d) depositing a base ohmic metal photoresist on said emitter mesa, photoresist and said exposed base layer; (e) patterning and developing said base ohmic metal photoresist to define base ohmic metal regions; (f) depositing base ohmic metal on said base ohmic metal regions; and (g) lifting off said base ohmic metal photoresist, as well as said emitter mesa photoresist leaving an ohmic metal region around said emitter mesa that is uniformly spaced relative to said emitter mesa.
Claim 2
Independent Claim
186 words
A method for controlling the spacing between an ohmic metal and an emitter mesa on an integrated circuit formed with a substrate and a plurality of vertically stacked epitaxial layers, including a base layer and an emitter layer formed on top, the method comprising the steps of: (a) depositing an emitter mesa photoresist on top of said emitter layer; (b) forming said emitter mesa photoresist to have a re-entrant profile, defining an overhand on top of said emitter mesa; (c) etching said emitter layer to form an emitter mesa and exposing said base layer, said emitter mesa photoresist overhanging said emitter mesa with said re-entrant profile after said etching; (d) depositing a base ohmic metal photoresist on said emitter mesa, photoresist and said exposed base layer; (e) patterning and developing said base ohmic metal photoresist to define base ohmic metal regions; (f) depositing base ohmic metal on said base ohmic metal regions; and (g) lifting off said base ohmic metal photoresist, as well as said emitter mesa photoresist leaving an ohmic metal region around said emitter mesa that is uniformly spaced relative to said emitter mesa.
Claim 3
Dependent Claim
16 words
A method as recited in claim 1, wherein said emitter mesa photoresist is a negative photoresist.
Claim 4
Dependent Claim
15 words
A method as recited in claim 2, wherein said negative photoresist is an i-line photoresist.
Claim 5
Dependent Claim
17 words
A method as recited in claim 1, wherein said base ohmic metal photoresist is a negative photoresist.
Claim 6
Dependent Claim
15 words
A method as recited in claim 4, wherein said negative photoresist is an i-line photoresist.
Claim 7
Dependent Claim
13 words
A method as recited in claim 1, wherein said etching is wet etching.
Claim 8
Dependent Claim
14 words
The method as recited in claim 1, wherein said etching is isotropic dry etching.
Claim 9
Dependent Claim
24 words
The method as recited in claim 1, wherein said step of forming said emitter mesa photoresist includes exposing and developing said emitter mesa photoresist.
Claim 10
Dependent Claim
30 words
The method as recited in claim 8, further including the steps of baking said emitter mesa photoresist prior to said step of exposing and prior to said step of developing.
Claim 11
Dependent Claim
24 words
The method as recited in claim 9, further including the step of baking said emitter mesa photoresist after said steps of exposing and developing.
Claim 12
Dependent Claim
24 words
The method as recited in claim 1, wherein said emitter mesa photoresist is formed with a thickness in the range of 3000 A-5000 A.
Claim 13
Dependent Claim
18 words
The method as recited in claim 1, further including the step of descumming prior to said etching step.
Claim 14
Dependent Claim
23 words
The method as recited in claim 1, further including the step of descumming after said step of developing said base ohmic metal resist.
Claim 15
Independent Claim
198 words
A method for controlling the spacing of the base ohmic metal relative to an emitter mesa on a heterojunction bipolar transistor (HBT) having a substrate and a plurality of vertically stacked epitaxial layers including a base layer, and an emitter layer formed on top, the method comprising the steps of: (a) depositing an emitter mesa photoresist on top of said emitter layer; (b) patterning and developing said emitter mesa photoresist with a re-entrant profile; (c) etching said emitter layer to form said emitter mesa and exposing a portion of said base layer, leaving intact said emitter mesa photoresist with said re-entrant profile; (d) depositing a phase ohmic metal photoresist on top of said exposed base layer and said emitter mesa photoresist; (e) patterning and developing said base ohmic photoresist to define base ohmic metal regions; (f) depositing a base ohmic metal on said emitter mesa photresist, said base ohmic metal photoresist and said exposed portion of said base layer; and (g) lifting off said base ohmic metal deposited on said emitter mesa and base ohmic metal photoresists along with said emitter mesa and second base ohmic metal photoresist leaving a base ohmic metal region around said emitter mesa.
Claim 16
Independent Claim
198 words
A method for controlling the spacing of the base ohmic metal relative to an emitter mesa on a heterojunction bipolar transistor (HBT) having a substrate and a plurality of vertically stacked epitaxial layers including a base layer, and an emitter layer formed on top, the method comprising the steps of: (a) depositing an emitter mesa photoresist on top of said emitter layer; (b) patterning and developing said emitter mesa photoresist with a re-entrant profile; (c) etching said emitter layer to form said emitter mesa and exposing a portion of said base layer, leaving intact said emitter mesa photoresist with said re-entrant profile; (d) depositing a phase ohmic metal photoresist on top of said exposed base layer and said emitter mesa photoresist; (e) patterning and developing said base ohmic photoresist to define base ohmic metal regions; (f) depositing a base ohmic metal on said emitter mesa photresist, said base ohmic metal photoresist and said exposed portion of said base layer; and (g) lifting off said base ohmic metal deposited on said emitter mesa and base ohmic metal photoresists along with said emitter mesa and second base ohmic metal photoresist leaving a base ohmic metal region around said emitter mesa.
Claim 17
Dependent Claim
16 words
A method as recited in claim 14, wherein said emitter mesa photoresist is a negative photoresist.
Claim 18
Dependent Claim
15 words
A method as recited in claim 15, wherein said negative photoresist is an i-line photoresist.
Claim 19
Dependent Claim
17 words
A method as recited in claim 14, wherein said base ohmic metal photoresist is a negative photoresist.
Claim 20
Dependent Claim
15 words
A method as recited in claim 17, wherein said negative photoresist is an i-line photoresist.
Claim 21
Dependent Claim
13 words
A method as recited in claim 14, wherein said etching is wet etching.
Claim 22
Dependent Claim
14 words
The method as recited in claim 14, wherein said etching is isotropic dry etching.
Claim 23
Dependent Claim
24 words
The method as recited in claim 14, wherein said step of forming said emitter mesa photoresist includes exposing and developing said emitter mesa photoresist.
Claim 24
Dependent Claim
17 words
The method as recited in claim 21, wherein said emitter mesa photoresist is an i-line negative photoresist.
Claim 25
Dependent Claim
24 words
The method as recited in claim 22, further including the step of baking said emitter mesa photoresist after said steps of exposing and developing.
Claim 26
Dependent Claim
24 words
The method as recited in claim 14, wherein said emitter mesa photoresist is formed with a thickness in the range of 3000 A-5000 A.
Claim 27
Dependent Claim
18 words
The method as recited in claim 14, further including the step of descumming prior to said etching step.
Claim 28
Dependent Claim
23 words
The method as recited in claim 14, further including the step of descumming after said step of developing said base ohmic metal resist.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-11-29 | 2003-05-31 | 2003-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-29 | 2007-05-31 | 2007-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-29 | 2011-05-31 | 2011-11-30 | $7700.00 | Window Closed / Lapsed |