Patent US5986830A successfully refreshed from Google Patents.
US5986830A
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Read/write channel write precompensation system and method using one or more delay clocks
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1997-07-30
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Granted: 1999-11-16
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Expires: 2017-07-30
Abstract
Abstract An improved write precompensation circuit for a read/write channel circuit and system is provided. Multiple data input signals are provided, each being clocked by a different clock. The data input signals are then multiplexed. Two, three or more data clock delays may be utilized to provide two, three or more data delays to achieve the write precompensation. Only one edge of a signal need pass through a multiplexer before the multiplexer may change state. The amount of delay may be user programmable.
Inventors
- 👤 Jerrell P. Hein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:10
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/10009; G11B5/00; G11B5/02; G11B5/027; G11B5/035; G11B5/012
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
108 words
A write precompensation circuit, comprising: a data input terminal; a plurality of clock signals, at least one of said clock signals being delayed with respect to at least another of said clock signals, said clock signals being utilized to clock data at said data input terminal to generate a plurality of clocked data signals, at least one of said clocked data signals being delayed with respect to at least another of said clocked data signals; a multiplexer coupled to said clocked data signals; and a data output terminal coupled to said multiplexer, said multiplexer providing at least one of said clocked data signals to said data output terminal.
Claim 2
Dependent Claim
108 words
A write precompensation circuit, comprising: a data input terminal; a plurality of clock signals, at least one of said clock signals being delayed with respect to at least another of said clock signals, said clock signals being utilized to clock data at said data input terminal to generate a plurality of clocked data signals, at least one of said clocked data signals being delayed with respect to at least another of said clocked data signals; a multiplexer coupled to said clocked data signals; and a data output terminal coupled to said multiplexer, said multiplexer providing at least one of said clocked data signals to said data output terminal.
Claim 3
Dependent Claim
37 words
The circuit of claim 1, further comprising: a plurality of latch circuits coupled to said data input terminal and said plurality of clock signals, said latch circuits providing said plurality of clocked data signals to said multiplexer.
Claim 4
Dependent Claim
10 words
The circuit of claim 2, wherein said latches comprise flip-flops.
Claim 5
Dependent Claim
34 words
The circuit of claim 2, wherein said plurality of clock signals includes at least one undelayed clock signal and the remaining of said plurality of clock signals being generated from said undelayed clock signal.
Claim 6
Dependent Claim
26 words
The circuit of claim 1, said plurality of clock signals comprising at least one reference delay clock signal and at least one programmable delay clock signal.
Claim 7
Dependent Claim
100 words
The circuit of claim 1, further comprising: an undelayed clock signal; a plurality of delay circuits, said delay circuits comprising at least one reference delay circuit and at least one programmable delay circuit, said undelayed clock signal being coupled to said plurality of delay circuits, each of said delay circuits generating at least one of said plurality of clock signals; and a plurality of latch circuits, each of said latch circuits coupled to at least one of said clock signals, said latch circuits also being coupled to said data, said latch circuits being clocked by said plurality of clock signals.
Claim 8
Independent Claim
69 words
A method of processing data in a write precompensation circuit, comprising: providing an input data stream; clocking said data stream by a plurality of clock signals to generate a plurality of clocked data streams, at least one of said clocked data streams being delayed with respect to at least another of said clocked data streams; and selecting at least one of said clocked data streams to provide output data.
Claim 9
Independent Claim
69 words
A method of processing data in a write precompensation circuit, comprising: providing an input data stream; clocking said data stream by a plurality of clock signals to generate a plurality of clocked data streams, at least one of said clocked data streams being delayed with respect to at least another of said clocked data streams; and selecting at least one of said clocked data streams to provide output data.
Claim 10
Dependent Claim
26 words
The method of claim 7, further comprising: providing said input data stream to a plurality of latches, said latches clocked by said plurality of clock signals.
Claim 11
Dependent Claim
27 words
The method of claim 8 wherein said plurality of clock signals comprises at least one reference delay clock signal and at least one programmable delay clock signal.
Claim 12
Dependent Claim
17 words
The method of claim 7 wherein said selecting step comprises multiplexing said plurality of clocked data streams.
Claim 13
Dependent Claim
16 words
The method of claim 10, at least one of said plurality of clock signals being programmable.
Claim 14
Dependent Claim
96 words
The method of claim 7, wherein said plurality of clock signals includes at least one undelayed clock signal, said method further comprising: providing said input data stream to a plurality of latch circuits; generating a plurality of precompensation clock signals from said undelayed clock signal, said plurality of precompensation clock signals comprising at least one reference delay precompensation clock signal and at least one programmable delay clock signal; clocking each of said plurality of latches by separate ones of said plurality of precompensation clock signals; and multiplexing outputs of said latches to provide said output data.
Claim 15
Independent Claim
148 words
A system for storing data, said system comprising: a data storage device; a system data input terminal for receiving data to be written to said data storage device; and a write channel circuit coupled to said system data input terminal and said data storage device, said write channel circuit including a data compensation circuit, said data compensation circuit comprising, a plurality of clock signals, at least one of said clock signals being delayed with respect to at least another of said clock signals, said clock signals being utilized to clock said data to generate a plurality of clocked data signals, at least one of said clocked data signals being delayed with respect to at least another of said clocked data input signals, and a multiplexer coupled to said clocked data signals, said multiplexer providing at least one of said clocked data signals at an output of said multiplexer.
Claim 16
Independent Claim
148 words
A system for storing data, said system comprising: a data storage device; a system data input terminal for receiving data to be written to said data storage device; and a write channel circuit coupled to said system data input terminal and said data storage device, said write channel circuit including a data compensation circuit, said data compensation circuit comprising, a plurality of clock signals, at least one of said clock signals being delayed with respect to at least another of said clock signals, said clock signals being utilized to clock said data to generate a plurality of clocked data signals, at least one of said clocked data signals being delayed with respect to at least another of said clocked data input signals, and a multiplexer coupled to said clocked data signals, said multiplexer providing at least one of said clocked data signals at an output of said multiplexer.
Claim 17
Dependent Claim
31 words
The system of claim 13, said write channel circuit further comprising a plurality of latches, each of said latches coupled to said data and one of said plurality of clock signals.
Claim 18
Dependent Claim
18 words
The system of claim 14, at least one of said plurality of clock signals having a programmable delay.
Claim 19
Dependent Claim
100 words
The system of claim 13, further comprising: an undelayed clock signal; a plurality of delay circuits, said delay circuits comprising at least one reference delay circuit and at least one programmable delay circuit, said undelayed clock signal being coupled to said plurality of delay circuits, each of said delay circuits generating at least one of said plurality of clock signals; and a plurality of latch circuits, each of said latch circuits coupled to at least one of said clock signals, said latch circuits also being coupled to said data, said latch circuits being clocked by said plurality of clock signals.
Claim 20
Independent Claim
102 words
A method of operating a system for writing data to a data storage device, said method comprising: providing a data storage device; providing an input data stream to be written to said data storage device; and processing said input data stream to provide write precompensation, said processing comprising, clocking said input data stream by a plurality of clock signals to generate a plurality of clocked data streams, at least one of said clocked data streams being delayed with respect to at least another of said clocked data streams, and selecting at least one of said clocked data streams to provide output data.
Claim 21
Independent Claim
102 words
A method of operating a system for writing data to a data storage device, said method comprising: providing a data storage device; providing an input data stream to be written to said data storage device; and processing said input data stream to provide write precompensation, said processing comprising, clocking said input data stream by a plurality of clock signals to generate a plurality of clocked data streams, at least one of said clocked data streams being delayed with respect to at least another of said clocked data streams, and selecting at least one of said clocked data streams to provide output data.
Claim 22
Dependent Claim
14 words
The method of claim 17, said selecting step comprising multiplexing said clocked data streams.
Claim 23
Dependent Claim
33 words
The method of claim 18, said clocking step comprising providing said input data stream to a plurality of latches and clocking each of said latches by one of said plurality of clock signals.
Claim 24
Dependent Claim
88 words
The method of claim 17, further comprising: providing at least one undelayed clock signal; providing said input data stream to a plurality of latch circuits; generating a plurality of precompensation clock signals from said undelayed clock signal, said plurality of precompensation clock signals comprising at least one reference delay precompensation clock signal and at least one programmable delay clock signal; clocking each of said plurality of latches by separate ones of said plurality of precompensation clock signals; and multiplexing outputs of said latches to provide said output data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-15 | 2003-05-17 | 2003-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-15 | 2007-05-17 | 2007-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-15 | 2011-05-17 | 2011-11-16 | $7700.00 | Window Closed / Lapsed |