US5726990A
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Multiplexer and demultiplexer
Assignee: Mitsubishi Electric Corp
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Filing: 1996-04-08
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Granted: 1998-03-10
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Expires: 2016-04-08
Abstract
Abstract A multiplexer includes an n-th stage as a final output stage (n=integer, 2≦n); j stages (j=integer, 1≦j≦n-1), the n-th stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the clock signal with the serial data; and a j-th stage including m n-j-1 (m=integer, 2≦m) multiplexer blocks, each multiplexer block including D flip-flops and having data input terminals for receiving m parallel data inputs and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, and converting the parallel data into serial data in response to the second clock signal. The multiplexer further includes a variable delay circuit connected to the data input terminal of each multiplexer block in one of the second to the n-th stages for delaying the data input by a variable delay time. Therefore, even when the delay times of the constituents of the circuit vary due to device parameters or temperature, the timing of the data input can be adjusted by the variable delay circuit.
Inventors
- 👤 Masaaki Shimada
- 👤 Norio Higashisaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:06
CPC Classifications
H; H03; H03M; H03M9/00; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0685
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
208 words
A multiplexer comprising: an n-th stage as a final output stage (n=integer, 2≦n); j stages (j=integer, 1≦j≦n-1), the n-th stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the serial data with the first clock signal, a j-th stage including m n-j-1 (m=integer, 2≦m) multiplexer blocks, each multiplexer block comprising a plurality of D flip-flops and having data input terminals for receiving m inputs of parallel data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each multiplexer block converting parallel data into serial data in response to the second clock signal, a multiplexer block in the j-th stage being connected to a multiplexer block in the (j+1)-th stage so that the serial data output from a multiplexer block in the j-th stage is applied as parallel data input to a multiplexer block in the (j+1)-th stage; and a variable delay circuit connected to a data input terminal of each multiplexer block in one of the second to the n-th stages, the variable delay circuit delaying data input by a variable delay time.
Claim 2
Dependent Claim
208 words
A multiplexer comprising: an n-th stage as a final output stage (n=integer, 2≦n); j stages (j=integer, 1≦j≦n-1), the n-th stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the serial data with the first clock signal, a j-th stage including m n-j-1 (m=integer, 2≦m) multiplexer blocks, each multiplexer block comprising a plurality of D flip-flops and having data input terminals for receiving m inputs of parallel data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each multiplexer block converting parallel data into serial data in response to the second clock signal, a multiplexer block in the j-th stage being connected to a multiplexer block in the (j+1)-th stage so that the serial data output from a multiplexer block in the j-th stage is applied as parallel data input to a multiplexer block in the (j+1)-th stage; and a variable delay circuit connected to a data input terminal of each multiplexer block in one of the second to the n-th stages, the variable delay circuit delaying data input by a variable delay time.
Claim 3
Dependent Claim
46 words
The multiplexer of claim 1 further including: means for monitoring data output from the data output terminal of the D flip-flop in the n-th stage; and means for controlling the delay time of the variable delay circuit with a control signal in response to the monitoring.
Claim 4
Dependent Claim
73 words
The multiplexer of claim 2 wherein the variable delay circuit comprises: a plurality of lines respectively comprising different numbers of buffers providing different delay times, the lines being arranged in parallel with each other; and a selector for selecting one of the lines in response to the control signal supplied from the means for controlling the delay time, the selector being connected to the lines and to the means for controlling delay time.
Claim 5
Dependent Claim
38 words
The multiplexer of claim 2 wherein the variable delay circuit comprises at least a variable delay buffer connected to the means for controlling the delay time for varying the variable delay time in response to the control signal.
Claim 6
Dependent Claim
50 words
The multiplexer of claim 4 wherein the variable delay buffer comprises a source follower buffer including a current supply transistor in which the delay time is controlled by controlling a gate voltage of the current supply transistor with the control signal supplied from the means for controlling the delay time.
Claim 7
Dependent Claim
223 words
A multiplexer comprising: an n-th stage as a final output stage (n=integer, 2≦n); j stages (j=integer, 1≦j≦n-1), the n-th stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the serial data with the first clock signal, a j-th stage including m n-j-1 (m=integer, 2≦m) multiplexer blocks, each multiplexer block comprising a plurality of D flip-flops and having data input terminals for receiving m inputs of parallel data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each multiplexer block converting parallel data into serial data in response to the second clock signal, a multiplexer block in the j-th stage being connected to a multiplexer block in the (j+1)-th stage so that the serial data output from a multiplexer block in the j-th stage is applied as parallel data input to a multiplexer block in the (j+1)-th stage; and a variable delay circuit connected to the clock input terminal of each multiplexer block in one of the first to the (n-1)th stages or to the clock input terminal of the D flip-flop in the n-th stage, the variable delay circuit delaying the clock input by a variable delay time.
Claim 8
Dependent Claim
223 words
A multiplexer comprising: an n-th stage as a final output stage (n=integer, 2≦n); j stages (j=integer, 1≦j≦n-1), the n-th stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the serial data with the first clock signal, a j-th stage including m n-j-1 (m=integer, 2≦m) multiplexer blocks, each multiplexer block comprising a plurality of D flip-flops and having data input terminals for receiving m inputs of parallel data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each multiplexer block converting parallel data into serial data in response to the second clock signal, a multiplexer block in the j-th stage being connected to a multiplexer block in the (j+1)-th stage so that the serial data output from a multiplexer block in the j-th stage is applied as parallel data input to a multiplexer block in the (j+1)-th stage; and a variable delay circuit connected to the clock input terminal of each multiplexer block in one of the first to the (n-1)th stages or to the clock input terminal of the D flip-flop in the n-th stage, the variable delay circuit delaying the clock input by a variable delay time.
Claim 9
Dependent Claim
223 words
A multiplexer comprising: an n-th stage as a final stage (n=integer, 2≦n); h stages (h=integer, 1≦h≦n-1), the n-th stage including a multiplexer block comprising a plurality of D flip-flops and having a clock input terminal for receiving a first clock signal, a data input terminal for receiving m (m=integer, 2≦m) inputs of parallel data, and a data output terminal, the multiplexer block converting the parallel data into serial data in response to the first clock signal, an h-th stage including m n-h multiplexer blocks, each multiplexer block comprising a plurality of D flip-flops and having data input terminals for receiving m inputs of parallel data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each multiplexer block converting parallel data into serial data in response to the second clock signal, and a multiplexer block in the h-th stage being connected to a multiplexer block in the (h+1)-th stage so that the serial data output from a multiplexer block in the h-th stage is applied as parallel data input to a multiplexer block in the (h+1)-th stage; and a variable delay circuit connected to the data input terminal of each multiplexer block in one of the second to the n-th stages, the variable delay circuit delaying data input by a variable delay time.
Claim 10
Dependent Claim
223 words
A multiplexer comprising: an n-th stage as a final stage (n=integer, 2≦n); h stages (h=integer, 1≦h≦n-1), the n-th stage including a multiplexer block comprising a plurality of D flip-flops and having a clock input terminal for receiving a first clock signal, a data input terminal for receiving m (m=integer, 2≦m) inputs of parallel data, and a data output terminal, the multiplexer block converting the parallel data into serial data in response to the first clock signal, an h-th stage including m n-h multiplexer blocks, each multiplexer block comprising a plurality of D flip-flops and having data input terminals for receiving m inputs of parallel data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each multiplexer block converting parallel data into serial data in response to the second clock signal, and a multiplexer block in the h-th stage being connected to a multiplexer block in the (h+1)-th stage so that the serial data output from a multiplexer block in the h-th stage is applied as parallel data input to a multiplexer block in the (h+1)-th stage; and a variable delay circuit connected to the data input terminal of each multiplexer block in one of the second to the n-th stages, the variable delay circuit delaying data input by a variable delay time.
Claim 11
Dependent Claim
46 words
The multiplexer of claim 3 further including: means for monitoring data output from the data output terminal of the multiplexer block in the n-th stage; and means for controlling the delay time of the variable delay circuit with a control signal in response to the monitoring.
Claim 12
Dependent Claim
238 words
A multiplexer comprising: an n-th stage as a final stage (n=integer, 2≦n); h stages (h=integer, 1≦h≦n-1), the n-th stage including a multiplexer block comprising a plurality of D flip-flops and having a clock input terminal for receiving a first clock signal, a data input terminal for receiving m (m=integer, 2≦m) inputs of parallel data, and a data output terminal, the multiplexer block converting the parallel data into serial data in response to the first clock signal; an h-th stage including m n-h multiplexer blocks, each multiplexer block comprising a plurality of D flip-flops and having data input terminals for receiving m inputs of parallel data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each multiplexer block converting parallel data into serial data in response to the second clock signal, and a multiplexer block in the h-th stage being connected to a multiplexer block in the (h+1)-th stage so that the serial data output from a multiplexer block in the h-th stage is applied as parallel data input to a multiplexer block in the (h+1)-th stage; and a variable delay circuit connected to a data input terminal of each multiplexer block in one of the first to the (n-1) stages or to the clock input terminal of the multiplexer block in the n-th stage, the variable delay circuit delaying the clock input by a variable delay time.
Claim 13
Dependent Claim
238 words
A multiplexer comprising: an n-th stage as a final stage (n=integer, 2≦n); h stages (h=integer, 1≦h≦n-1), the n-th stage including a multiplexer block comprising a plurality of D flip-flops and having a clock input terminal for receiving a first clock signal, a data input terminal for receiving m (m=integer, 2≦m) inputs of parallel data, and a data output terminal, the multiplexer block converting the parallel data into serial data in response to the first clock signal; an h-th stage including m n-h multiplexer blocks, each multiplexer block comprising a plurality of D flip-flops and having data input terminals for receiving m inputs of parallel data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each multiplexer block converting parallel data into serial data in response to the second clock signal, and a multiplexer block in the h-th stage being connected to a multiplexer block in the (h+1)-th stage so that the serial data output from a multiplexer block in the h-th stage is applied as parallel data input to a multiplexer block in the (h+1)-th stage; and a variable delay circuit connected to a data input terminal of each multiplexer block in one of the first to the (n-1) stages or to the clock input terminal of the multiplexer block in the n-th stage, the variable delay circuit delaying the clock input by a variable delay time.
Claim 14
Dependent Claim
202 words
A demultiplexer comprising; a first stage; i stages (i=integer, 2≦i≦n (n=integer, 2≦n), the first stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the serial data with the first clock signal, an i-th stage including m i-2 (m=integer, 2≦m) demultiplexer blocks, each demultiplexer block comprising a plurality of D flip-flops and having a data input terminal for receiving serial data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each demultiplexer block converting serial data into m parallel data outputs in response to the second clock signal, a demultiplexer block in the i-th stage being connected to a demultiplexer block in the (i-1)-th stage so that parallel data outputs from a demultiplexer block in the (i-1)-th stage is input to each demultiplexer block in the i-th stage as serial data; and a variable delay circuit connected to the data input terminal of each demultiplexer block in one of the second to the nth stages, the variable delay circuit delaying the data input by a variable delay time.
Claim 15
Dependent Claim
202 words
A demultiplexer comprising; a first stage; i stages (i=integer, 2≦i≦n (n=integer, 2≦n), the first stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the serial data with the first clock signal, an i-th stage including m i-2 (m=integer, 2≦m) demultiplexer blocks, each demultiplexer block comprising a plurality of D flip-flops and having a data input terminal for receiving serial data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each demultiplexer block converting serial data into m parallel data outputs in response to the second clock signal, a demultiplexer block in the i-th stage being connected to a demultiplexer block in the (i-1)-th stage so that parallel data outputs from a demultiplexer block in the (i-1)-th stage is input to each demultiplexer block in the i-th stage as serial data; and a variable delay circuit connected to the data input terminal of each demultiplexer block in one of the second to the nth stages, the variable delay circuit delaying the data input by a variable delay time.
Claim 16
Dependent Claim
46 words
The demultiplexer of claim 10 further including: means for monitoring data output from the data output terminals of the demultiplexer blocks in the n-th stage; and means for controlling the delay time of the variable delay circuit with a control signal in response to the monitoring.
Claim 17
Dependent Claim
73 words
The multiplexer of claim 11 wherein the variable delay circuit comprises: a plurality of lines respectively comprising different numbers of buffers providing different delay times, the lines being arranged in parallel with each other; and a selector for selecting one of the lines in response to the control signal supplied from the means for controlling the delay time, the selector being connected to the lines and to the means for controlling delay time.
Claim 18
Dependent Claim
38 words
The multiplexer of claim 11 wherein the variable delay circuit comprises at least a variable delay buffer connected to the means for controlling the delay time for varying the variable delay time in response to the control signal.
Claim 19
Dependent Claim
50 words
The demultiplexer of claim 13 wherein the variable delay buffer comprises a source follower buffer including a current supply transistor in which the delay time is controlled by controlling a gate voltage of the current supply transistor with the control signal supplied from the means for controlling the delay time.
Claim 20
Dependent Claim
216 words
A demultiplexer comprising: a first stage; i stages (i=integer, 2≦i≦n (n=integer, 2≦n)), the first stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the serial data with the first clock signal, an i-th stage including m i-2 (m=integer, 2≦m) demultiplexer blocks, each demultiplexer block comprising a plurality of D flip-flops and having a data input terminal for receiving serial data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each demultiplexer block converting serial data into m parallel data outputs in response to the second clock signal, a demultiplexer block in the i-th stage being connected to a demultiplexer block in the (i-1)-th stage so that parallel data outputs from a demultiplexer block in the (i-1)-th stage is input to each demultiplexer block in the i-th stage as serial data; and a variable delay circuit connected to the clock input terminal of each demultiplexer block in one of the second to the nth stages or to the clock input terminal of the D flip-flop in the first stage, the variable delay circuit delaying the clock input by a variable delay time.
Claim 21
Dependent Claim
216 words
A demultiplexer comprising: a first stage; i stages (i=integer, 2≦i≦n (n=integer, 2≦n)), the first stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the serial data with the first clock signal, an i-th stage including m i-2 (m=integer, 2≦m) demultiplexer blocks, each demultiplexer block comprising a plurality of D flip-flops and having a data input terminal for receiving serial data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each demultiplexer block converting serial data into m parallel data outputs in response to the second clock signal, a demultiplexer block in the i-th stage being connected to a demultiplexer block in the (i-1)-th stage so that parallel data outputs from a demultiplexer block in the (i-1)-th stage is input to each demultiplexer block in the i-th stage as serial data; and a variable delay circuit connected to the clock input terminal of each demultiplexer block in one of the second to the nth stages or to the clock input terminal of the D flip-flop in the first stage, the variable delay circuit delaying the clock input by a variable delay time.
Claim 22
Dependent Claim
217 words
A demultiplexer comprising: a first stage; k stages (k=integer, 2≦k≦n (n=integer, 2≦n)), the first stage including a demultiplexer block comprising a plurality of D flip-flops and having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the demultiplexer block converting the serial data into m (m=integer 2≦m) parallel data outputs in response to the first clock signal, a k-th stage including m k-1 demultiplexer blocks, each demultiplexer block comprising a plurality of D flip-flops and having a data input terminal for receiving serial data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each demultiplexer block converting serial data into m parallel data outputs in response to the second clock signal, a demultiplexer block in the k-th stage being connected to a demultiplexer block in a (k-1)-th stage so that parallel data output from a demultiplexer block in the (k-1)-th stage is input to each demultiplexer block in the k-th stage as the serial data; and a variable delay circuit connected to the data input terminal of each demultiplexer block in one of the second to the nth stages, the variable delay circuit delaying the data input by a variable delay time.
Claim 23
Dependent Claim
217 words
A demultiplexer comprising: a first stage; k stages (k=integer, 2≦k≦n (n=integer, 2≦n)), the first stage including a demultiplexer block comprising a plurality of D flip-flops and having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the demultiplexer block converting the serial data into m (m=integer 2≦m) parallel data outputs in response to the first clock signal, a k-th stage including m k-1 demultiplexer blocks, each demultiplexer block comprising a plurality of D flip-flops and having a data input terminal for receiving serial data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each demultiplexer block converting serial data into m parallel data outputs in response to the second clock signal, a demultiplexer block in the k-th stage being connected to a demultiplexer block in a (k-1)-th stage so that parallel data output from a demultiplexer block in the (k-1)-th stage is input to each demultiplexer block in the k-th stage as the serial data; and a variable delay circuit connected to the data input terminal of each demultiplexer block in one of the second to the nth stages, the variable delay circuit delaying the data input by a variable delay time.
Claim 24
Dependent Claim
49 words
The demultiplexer of claim 16 further including: means for monitoring data output from the data output terminals of the demultiplexer blocks in the n-th stage; and means for controlling the delay time of the variable delay circuit with a control signal in response to the result of the monitoring.
Claim 25
Dependent Claim
231 words
A demultiplexer comprising: a first stage; k stages (k=integer, 2≦k≦n (n=integer, 2≦n)), the first stage including a demultiplexer block comprising a plurality of D flip-flops and having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the demultiplexer block converting the serial data into m (m=integer, 2≦m) parallel data outputs in response to the first clock signal; a k-th stage including m k-1 demultiplexer blocks, each demultiplexer block comprising a plurality of D flip-flops and having a data input terminal for receiving serial data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each demultiplexer block converting serial data into m parallel data outputs in response to the second clock signal, a demultiplexer block in the k-th stage being connected to a demultiplexer block in a (k-1)-th stage so that parallel data output from a demultiplexer block in the (k-1)-th stage is input to each demultiplexer block in the k-th stage as the serial data; and a variable delay circuit connected to the clock input terminal of each demultiplexer block in any of the second to the nth stages or to the clock input terminal of the D flip-flop in the first stage, the variable delay circuit delaying the clock input by a variable delay time.
Claim 26
Dependent Claim
231 words
A demultiplexer comprising: a first stage; k stages (k=integer, 2≦k≦n (n=integer, 2≦n)), the first stage including a demultiplexer block comprising a plurality of D flip-flops and having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the demultiplexer block converting the serial data into m (m=integer, 2≦m) parallel data outputs in response to the first clock signal; a k-th stage including m k-1 demultiplexer blocks, each demultiplexer block comprising a plurality of D flip-flops and having a data input terminal for receiving serial data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each demultiplexer block converting serial data into m parallel data outputs in response to the second clock signal, a demultiplexer block in the k-th stage being connected to a demultiplexer block in a (k-1)-th stage so that parallel data output from a demultiplexer block in the (k-1)-th stage is input to each demultiplexer block in the k-th stage as the serial data; and a variable delay circuit connected to the clock input terminal of each demultiplexer block in any of the second to the nth stages or to the clock input terminal of the D flip-flop in the first stage, the variable delay circuit delaying the clock input by a variable delay time.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-03-09 | 2001-09-08 | 2002-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-09 | 2005-09-08 | 2006-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-09 | 2009-09-08 | 2010-03-10 | $7700.00 | Window Closed / Lapsed |