Semiconductor integrated circuit device having multi-level wiring capacitor structures

Claim 1

A semiconductor integrated circuit device comprising: a peripheral circuit part including an I/O control circuit portion and a decoder portion; a memory cell array portion; a semiconductor region of an insulated gate field effect transistor formed in said memory cell array portion, wherein said semiconductor region is electrically connected with a lower electrode of a capacitor formed on a plurality of interlayer insulating films formed on said insulated gate field effect transistor, through plugs formed in each of said plurality of interlayer insulating films and directly connected in sequence, wherein (i) an upper surface of each of a plurality of interlayer insulating films is substantially flat in areas of a peripheral circuit part and of a memory cell array portion, and (ii) a height of the upper surface of each of a plurality of interlayer insulating films in said peripheral circuit part and a height of the upper surface of each of a plurality of interlayer insulating films in said memory cell array portion are substantially equal; a plurality of plugs formed in said peripheral circuit part and mutually connected in sequence through patterned conductors, wherein each of said plurality of interlayer insulating films has two kinds of plugs formed therein including (i) a plug having substantially a same height as a thickness of an interlayer insulating film corresponding thereto in an area of said memory cell array portion, and (ii) a plug having a height lower than a thickness of an interlayer insulating film corresponding thereto, formed on a patterned conductor in an area of the peripheral circuit part; and a plurality of capacitors formed in said memory cell array portion and placed above all wiring layers.