Patent US5985731A successfully refreshed from Google Patents.
US5985731A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming a semiconductor device having a capacitor structure
Assignee: NXP USA Inc
•
Filing: 1998-08-17
•
Granted: 1999-11-16
•
Expires: 2018-08-17
Abstract
Abstract A method of forming a stacked capacitor structure in a semiconductor device, having metal electrode plates. After depositing the bottom electrode layer (26) and the dielectric layer (28) of the capacitor, a rough patterning step is carried out to roughly pattern or shape the bottom electrode layer and the dielectric layer, and to expose the underlying interlayer dielectric (18). A top electrode layer (32) is then blanket deposited, and another, more precise etching step is carried out to form the final shape of the capacitor element, while leaving behind a portion of the top electrode layer on the interlayer dielectric, which forms a metal interconnect (36). In one embodiment, the electrode layers are comprised of materials having a conductivity greater than doped silicon (either poly or monocrystalline), such as a metal.
Inventors
- 👤 Kenneth Chia-Kun Weng
- 👤 Christopher Sterling Lohn
- 👤 Der-Gao Lin
- 👤 Kevin Yun-Kang Wu
- 👤 Jeffrey D. Ganger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:13
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D88/00; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/071; H10W20/081
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
148 words
A method for forming a semiconductor device, comprising the steps of: providing a semiconductor substrate; forming an interlayer dielectric overlying the semiconductor substrate; depositing a bottom electrode layer to overlie the interlayer dielectric; depositing dielectric layer to overlie the bottom electrode layer; selectively etching the bottom electrode layer and the dielectric layer, to partially remove the bottom electrode layer and the dielectric layer and expose a portion of the interlayer dielectric; depositing a top electrode layer so as to overlie the dielectric layer and the interlayer dielectric; and etching the top electrode layer, the dielectric layer and the bottom electrode layer, to form a top electrode plate, a dielectric plate, and a bottom electrode plate, respectively, to form a capacitor structure, wherein during etching of the top electrode layer, at least one portion of the top electrode layer overlying the interlayer dielectric remains to define a metal interconnect.
Claim 2
Independent Claim
148 words
A method for forming a semiconductor device, comprising the steps of: providing a semiconductor substrate; forming an interlayer dielectric overlying the semiconductor substrate; depositing a bottom electrode layer to overlie the interlayer dielectric; depositing dielectric layer to overlie the bottom electrode layer; selectively etching the bottom electrode layer and the dielectric layer, to partially remove the bottom electrode layer and the dielectric layer and expose a portion of the interlayer dielectric; depositing a top electrode layer so as to overlie the dielectric layer and the interlayer dielectric; and etching the top electrode layer, the dielectric layer and the bottom electrode layer, to form a top electrode plate, a dielectric plate, and a bottom electrode plate, respectively, to form a capacitor structure, wherein during etching of the top electrode layer, at least one portion of the top electrode layer overlying the interlayer dielectric remains to define a metal interconnect.
Claim 3
Dependent Claim
38 words
The method of claim 1, further comprising steps of: forming a second interlayer dielectric overlying the top electrode layer; and providing a via extending through the second interlayer dielectric and making electrical contact with the top electrode plate.
Claim 4
Dependent Claim
27 words
The method of claim 1, wherein the interlayer dielectric has a conductive portion, and the bottom electrode layer is deposited so as to overlie the conductive portion.
Claim 5
Dependent Claim
36 words
The method of claim 3, wherein the semiconductor substrate has a transistor structure formed therein, and the conductive portion of the interlayer dielectric is a contact extending through the interlayer dielectric and contacting the transistor structure.
Claim 6
Dependent Claim
50 words
The method of claim 4, wherein the contact is formed by: blanket depositing a conductive layer over the interlayer dielectric, so as to fill an opening therein; and polishing the conductive layer to remove a first portion overlying the interlayer dielectric and leaving behind a second portion in the opening.
Claim 7
Dependent Claim
23 words
The method of claim 4, wherein the contact comprises at least one material selected from the group consisting of W, Ti, and Cu.
Claim 8
Dependent Claim
28 words
The method of claim 1, wherein the bottom electrode plate and the top electrode plate comprise a conductive material having a resistivity less than 1×10 -5 ohm cm.
Claim 9
Dependent Claim
23 words
The method of claim 7, wherein the top electrode plate comprises at least one component from a group consisting of Cu and Al.
Claim 10
Dependent Claim
26 words
The method of claim 7, wherein the bottom electrode plate comprises at least one component from a group consisting of Ti, Ta, W, Cu, and Al.
Claim 11
Dependent Claim
21 words
The method of claim 9, wherein bottom electrode plate comprises a nitride or silicide of Ti, Ta, W, Cu, or Al.
Claim 12
Dependent Claim
22 words
The method of claim 1, wherein the dielectric layer comprises at least one material from a group consisting of nitrides and oxides.
Claim 13
Dependent Claim
24 words
The method of claim 1, wherein the dielectric layer comprises at least one material from a group consisting of silicon nitride and silicon oxide.
Claim 14
Dependent Claim
32 words
The method of claim 1, further comprising forming a protective layer overlying the dielectric layer prior to the step of selectively etching, wherein the step of selectively etching etches the protective layer.
Claim 15
Dependent Claim
22 words
The method of claim 13, wherein the protective layer comprises at least one material from a group consisting of nitrides and silicides.
Claim 16
Independent Claim
141 words
A method for forming a semiconductor device, comprising the steps of: providing a semiconductor substrate; forming an interlayer dielectric overlying the semiconductor substrate; depositing a bottom electrode layer to overlie the interlayer dielectric; depositing dielectric layer to overlie the bottom electrode layer; selectively etching the bottom electrode layer and the dielectric layer, to partially remove the bottom electrode layer and the dielectric layer and expose a portion of the interlayer dielectric; depositing a top electrode layer so as to overlie the dielectric layer and the interlayer dielectric; and etching the top electrode layer, the dielectric layer and the bottom electrode layer, to form a top electrode plate, a dielectric plate, and a bottom electrode plate to form a capacitor structure, wherein the top electrode plate and the bottom electrode plate have a resistivity less than less than 1×10 -5 ohm cm.
Claim 17
Independent Claim
141 words
A method for forming a semiconductor device, comprising the steps of: providing a semiconductor substrate; forming an interlayer dielectric overlying the semiconductor substrate; depositing a bottom electrode layer to overlie the interlayer dielectric; depositing dielectric layer to overlie the bottom electrode layer; selectively etching the bottom electrode layer and the dielectric layer, to partially remove the bottom electrode layer and the dielectric layer and expose a portion of the interlayer dielectric; depositing a top electrode layer so as to overlie the dielectric layer and the interlayer dielectric; and etching the top electrode layer, the dielectric layer and the bottom electrode layer, to form a top electrode plate, a dielectric plate, and a bottom electrode plate to form a capacitor structure, wherein the top electrode plate and the bottom electrode plate have a resistivity less than less than 1×10 -5 ohm cm.
Claim 18
Dependent Claim
39 words
The method of claim 15, wherein the top electrode plate comprises a material from a group consisting of Cu and Al, and the bottom electrode plate comprises a material from a group consisting of Ti, Ta, W, Cu, Al.
Claim 19
Dependent Claim
21 words
The method of claim 16, wherein bottom electrode plate comprises a nitride or silicide of Ti, Ta, W, Cu, or Al.
Claim 20
Independent Claim
210 words
A method for forming a semiconductor device, comprising the steps of: providing a semiconductor substrate; forming an interlayer dielectric overlying the semiconductor substrate, the interlayer dielectric having a first contact and a second contact extending therethrough; depositing a bottom electrode layer to overlie the first contact and the interlayer dielectric, such that electrical connection is made between the bottom electrode layer and the first contact; depositing dielectric layer to overlie the bottom electrode layer; selectively etching the bottom electrode layer and the dielectric layer, to partially remove the bottom electrode layer and the dielectric layer and expose a portion of the interlayer dielectric and the second contact; blanket depositing a top electrode layer so as to overlie the dielectric layer and the interlayer dielectric, said top electrode layer comprising a material from a group consisting of Al and Cu; and etching the top electrode layer, the dielectric layer and the bottom electrode layer, to form a top electrode plate, a dielectric plate, and a bottom electrode plate to form a capacitor structure that overlies and is in electrical connection with the first contact, wherein during etching of the top electrode layer, a portion of the top electrode layer overlying the second contact is left behind to define a metal interconnect.
Claim 21
Independent Claim
210 words
A method for forming a semiconductor device, comprising the steps of: providing a semiconductor substrate; forming an interlayer dielectric overlying the semiconductor substrate, the interlayer dielectric having a first contact and a second contact extending therethrough; depositing a bottom electrode layer to overlie the first contact and the interlayer dielectric, such that electrical connection is made between the bottom electrode layer and the first contact; depositing dielectric layer to overlie the bottom electrode layer; selectively etching the bottom electrode layer and the dielectric layer, to partially remove the bottom electrode layer and the dielectric layer and expose a portion of the interlayer dielectric and the second contact; blanket depositing a top electrode layer so as to overlie the dielectric layer and the interlayer dielectric, said top electrode layer comprising a material from a group consisting of Al and Cu; and etching the top electrode layer, the dielectric layer and the bottom electrode layer, to form a top electrode plate, a dielectric plate, and a bottom electrode plate to form a capacitor structure that overlies and is in electrical connection with the first contact, wherein during etching of the top electrode layer, a portion of the top electrode layer overlying the second contact is left behind to define a metal interconnect.
References Cited (Backward Citations)
US5065220A
Cited
US4638400A
Cited
US5109357A
Cited
US5196909A
Cited
DE4107165A1
Cited
US5119154A
Cited
US5300799A
Cited
US5185689A
Cited
US5381302A
Cited
US5479316A
Cited
US5576240A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-15 | 2003-05-17 | 2003-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-15 | 2007-05-17 | 2007-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-15 | 2011-05-17 | 2011-11-16 | $7700.00 | Window Closed / Lapsed |