US5982315A — Multi-loop Σ Δ analog to digital converter

Claim 1

Independent Claim 80 words

A sigma-delta analog-to-digital converter comprising: a plurality of loops coupled in cascade, wherein each loop is implemented with multi-sampling circuitry, said multi-sampling circuitry configured to implement filter functions and to sample a respective loop input signal at multiple phases of a clock signal; at least one feed-forward gain element, one gain element coupled between each pair of sequential loops; and a noise cancellation logic coupled to each of said plurality of loop, said noise cancellation logic providing a converter output.

Claim 2

Dependent Claim 80 words

A sigma-delta analog-to-digital converter comprising: a plurality of loops coupled in cascade, wherein each loop is implemented with multi-sampling circuitry, said multi-sampling circuitry configured to implement filter functions and to sample a respective loop input signal at multiple phases of a clock signal; at least one feed-forward gain element, one gain element coupled between each pair of sequential loops; and a noise cancellation logic coupled to each of said plurality of loop, said noise cancellation logic providing a converter output.

Claim 3

Dependent Claim 42 words

The converter of claim 1 wherein each loop comprises: at least one filter section, said at least one filter section coupled in cascade; and a quantizer coupled to a last filter section and to each of said at least one filter section.

Claim 4

Dependent Claim 13 words

The converter of claim 2 wherein each filter section comprises a resonator section.

Claim 5

Dependent Claim 22 words

The converter of claim 3 wherein each resonator section comprises: a summer coupled to said quantizer; a resonator coupled to said summer.

Claim 6

Dependent Claim 35 words

The converter of claim 1 wherein each loop includes at least one resonator, each resonator implemented as a delay cell based resonator, a lossless discrete integrator resonator, a Forward-Euler resonator, or a two-path interleaved resonator.

Claim 7

Dependent Claim 30 words

The converter of claim 1 wherein said multi-sampling circuitry is synthesized with an analog circuit technique selected from the group consisting of active-RC, gm-C, MOSFET-C, switched capacitor, and switched current.

Claim 8

Dependent Claim 18 words

The converter of claim 5 wherein said at least one resonator is implemented using double-sampling switched capacitor circuits.

Claim 9

Dependent Claim 52 words

The converter of claim 1 wherein each loop includes at least one delay cell resonator, each delay cell resonator comprises: a gain element; a summer coupled to said gain element; a first delay element coupled to said summer; and a second delay element coupled to said first delay element and said summer.

Claim 10

Dependent Claim 17 words

The converter of claim 8 wherein each delay element is implemented with a switched capacitor delay circuit.

Claim 11

Dependent Claim 28 words

The converter of claim 1 wherein said multi-sampling circuitry comprises double-sampling switched capacitor circuits that samples a respective loop input signal at alternative phases of a clock signal.

Claim 12

Dependent Claim 14 words

The converter of claim 1 wherein said multi-sampling circuitry comprises quadruple-sampling switched capacitor circuits.

Claim 13

Dependent Claim 33 words

The converter of claim 1 wherein each loop comprises: at least one resonator section; and a quantizer coupled to a last resonator section and to each of said at least one resonator section.

Claim 14

Dependent Claim 29 words

The converter of claim 12 wherein said resonator is selected from the group consisting of delay cell based resonator, lossless discrete integrator resonator, Forward-Euler resonator, and two-path interleaved resonator.

Claim 15

Dependent Claim 29 words

The converter of claim 13 wherein said resonator is synthesized with an analog circuit technique selected from the group consisting of active-RC, gm-C, MOSFET-C, switched capacitor, and switched current.

Claim 16

Dependent Claim 16 words

The converter of claim 12 wherein each resonator section is implemented using double-sampling switched capacitor circuits.

Claim 17

Dependent Claim 16 words

The converter of claim 12 wherein each resonator section is implemented using multi-sampling switched capacitor circuits.

Claim 18

Dependent Claim 119 words

A sigma-delta analog-to-digital converter comprising: a plurality of loops coupled in cascade, each loop including at least one delay circuit, wherein each delay circuit comprises an amplifier and two or more signal paths, each signal path comprising: a first switch; a capacitor coupled to said first switch; a second switch coupled to said capacitor and an AC ground; a third switch coupled to said first switch and an output of said amplifier; and a fourth switch coupled to said second switch and an input of said amplifier; wherein each signal path in a particular delay circuit is clocked by a set of clock signals having clock phases unique from those of other signal paths in the particular delay circuit.

Claim 19

Dependent Claim 119 words

A sigma-delta analog-to-digital converter comprising: a plurality of loops coupled in cascade, each loop including at least one delay circuit, wherein each delay circuit comprises an amplifier and two or more signal paths, each signal path comprising: a first switch; a capacitor coupled to said first switch; a second switch coupled to said capacitor and an AC ground; a third switch coupled to said first switch and an output of said amplifier; and a fourth switch coupled to said second switch and an input of said amplifier; wherein each signal path in a particular delay circuit is clocked by a set of clock signals having clock phases unique from those of other signal paths in the particular delay circuit.

Claim 20

Dependent Claim 151 words

A sigma-delta analog-to-digital converter comprising: a plurality of loops coupled in cascade, each loop including at least one delay cell and summer circuit, wherein each delay cell and summer circuit comprises an amplifier and two or more signal paths, each signal path comprising: a first switch; a first capacitor coupled to said first switch; a second switch coupled to said first capacitor and said AC ground; a third switch coupled to said first switch and said output of said loop in which said delay cell and summer circuit reside; a second capacitor coupled to said first capacitor; a fourth switch coupled to said second switch and an inverting input of said amplifier; a fifth switch coupled to said second capacitor and said n-inverting output of said amplifier; and a sixth switch coupled to said second capacitor and an inverting output of said amplifier within said delay circuit of said resonator section.

Claim 21

Dependent Claim 151 words

A sigma-delta analog-to-digital converter comprising: a plurality of loops coupled in cascade, each loop including at least one delay cell and summer circuit, wherein each delay cell and summer circuit comprises an amplifier and two or more signal paths, each signal path comprising: a first switch; a first capacitor coupled to said first switch; a second switch coupled to said first capacitor and said AC ground; a third switch coupled to said first switch and said output of said loop in which said delay cell and summer circuit reside; a second capacitor coupled to said first capacitor; a fourth switch coupled to said second switch and an inverting input of said amplifier; a fifth switch coupled to said second capacitor and said n-inverting output of said amplifier; and a sixth switch coupled to said second capacitor and an inverting output of said amplifier within said delay circuit of said resonator section.

Claim 22

Dependent Claim 30 words

The converter of claim 18 wherein amplifiers within said delay cell and summer circuits are selected from the group consisting of telescopic amplifier, folded-cascade amplifier, and two-stage pole splitting amplifier.

Claim 23

Dependent Claim 38 words

The converter of claim 18 wherein a gain of said delay cell and summer circuit is implemented as the ratio of capacitor values of said first capacitor and said second capacitor within said delay cell and summer circuit.

Claim 24

Dependent Claim 73 words

The converter of claim 18 further comprising: at least one feed-forward gain circuit, one feed-forward gain circuit coupled between each pair of sequential loops, each feed-forward gain circuit comprising at least two signal paths, each signal path comprising: a first switch; a capacitor coupled to said first switch; a second switch coupled to said first capacitor and said AC ground; and a third switch coupled to said second switch and said AC ground.

Claim 25

Dependent Claim 47 words

The converter of claim 21 wherein a gain of said feed-forward gain element is implemented as the ratio of capacitor values of said capacitor within said feed-forward gain circuit and said second capacitor within said delay cell and summer circuit to which said feed-forward gain circuit couples.

Claim 26

Dependent Claim 25 words

The converter of claim 18 wherein capacitor values of said capacitors within said delay cell and summer circuits are selected based on a noise calculation.

Claim 27

Dependent Claim 92 words

A sigma-delta analog-to-digital converter comprising: a plurality of loops coupled in cascade, wherein each loop includes a quantizer implemented with two comparators, wherein one comparator is clocked by a switching clock having a first phase and another comparator is clocked by a switching clock having a second phase, and wherein said comparators provide differential outputs; at least one feed-forward gain element, one gain element coupled between each pair of sequential loops; and a noise cancellation logic coupled to each of said plurality of loop, said noise cancellation logic providing a converter output.

Claim 28

Dependent Claim 92 words

A sigma-delta analog-to-digital converter comprising: a plurality of loops coupled in cascade, wherein each loop includes a quantizer implemented with two comparators, wherein one comparator is clocked by a switching clock having a first phase and another comparator is clocked by a switching clock having a second phase, and wherein said comparators provide differential outputs; at least one feed-forward gain element, one gain element coupled between each pair of sequential loops; and a noise cancellation logic coupled to each of said plurality of loop, said noise cancellation logic providing a converter output.

Claim 29

Dependent Claim 53 words

A bandpass sigma-delta analog-to-digital converter comprising: two or more loops coupled in cascade, each loop including a plurality of discrete delay elements; a feed-forward gain element, one gain element coupled between each pair of adjacent loops; and a noise cancellation logic coupled to each loop, said noise cancellation logic providing a converter output.

Claim 30

Dependent Claim 53 words

A bandpass sigma-delta analog-to-digital converter comprising: two or more loops coupled in cascade, each loop including a plurality of discrete delay elements; a feed-forward gain element, one gain element coupled between each pair of adjacent loops; and a noise cancellation logic coupled to each loop, said noise cancellation logic providing a converter output.

Claim 31

Dependent Claim 53 words

A sigma-delta analog-to-digital converter comprising: two or more loops coupled in cascade; and at least one feed-forward gain element, one feed-forward gain element coupled between each pair of sequential loops, wherein a bias current of at least one of said two or more loops can be adjusted based on a required dynamic range.

Claim 32

Dependent Claim 53 words

A sigma-delta analog-to-digital converter comprising: two or more loops coupled in cascade; and at least one feed-forward gain element, one feed-forward gain element coupled between each pair of sequential loops, wherein a bias current of at least one of said two or more loops can be adjusted based on a required dynamic range.

Claim 33

Dependent Claim 49 words

A sigma-delta analog-to-digital converter comprising: two or more loops coupled in cascade; and at least one feed-forward gain element, one feed-forward gain element coupled between each pair of sequential loops, wherein at least one of said two or more loops can be disabled based on a required dynamic range.

Claim 34

Dependent Claim 49 words

A sigma-delta analog-to-digital converter comprising: two or more loops coupled in cascade; and at least one feed-forward gain element, one feed-forward gain element coupled between each pair of sequential loops, wherein at least one of said two or more loops can be disabled based on a required dynamic range.

Claim 35

Dependent Claim 28 words

The converter of claim 24 further comprising: a noise cancellation logic coupled to each of said two or more loops, said noise cancellation logic providing a converter output.

Claim 36

Dependent Claim 27 words

The converter of claim 24 wherein each loop is implemented with multi-sampling circuitry that samples a respective loop input signal at multiple phases of a clock signal.

Claim 37

Dependent Claim 27 words

The converter of claim 24 wherein each loop is implemented with double-sampling circuitry that samples a respective loop input signal at alternative phases of a clock signal.

Claim 38

Dependent Claim 18 words

The converter of claim 24 wherein each loop is implemented with switched capacitor circuits or switched current circuits.

Claim 39

Dependent Claim 17 words

The converter of claim 26 wherein said two or more loops are configured as a MASH architecture.

Claim 40

Dependent Claim 22 words

The converter of claim 24 wherein said two or more loops are configured to provide bandpass sampling of a converter input signal.

Claim 41

Dependent Claim 42 words

A bandpass sigma-delta analog-to-digital converter comprising: two or more loops coupled in cascade, wherein each loop is implemented with two or more interleaved high-pass signal paths; and a feed-forward gain element, one feed-forward gain element coupled between each pair of sequential loops.

Claim 42

Dependent Claim 42 words

A bandpass sigma-delta analog-to-digital converter comprising: two or more loops coupled in cascade, wherein each loop is implemented with two or more interleaved high-pass signal paths; and a feed-forward gain element, one feed-forward gain element coupled between each pair of sequential loops.

Claim 43

Dependent Claim 33 words

The bandpass converter of claim 34 further comprising: a noise cancellation logic coupled to each loop, said noise cancellation logic combining outputs from said interleaved high-pass signal paths to provide a converter output.

Claim 44

Dependent Claim 24 words

The bandpass converter of claim 34 wherein said interleaved high-pass signal paths of each loop are clocked at different phases of a clock signal.

Claim 45

Dependent Claim 20 words

The bandpass converter of claim 34 wherein each interleaved high-pass signal path is implemented using at least one delay element.

Claim 46

Dependent Claim 60 words

A sigma-delta analog-to-digital converter comprising: a plurality of loops coupled in cascade, each loop including at least one filter section, wherein each filter section is implemented with multi-sampling circuitry that samples a respective filter input signal at multiple phases of a clock signal; and at least one feed-forward gain element, one gain element coupled between each pair of sequential loops.

Claim 47

Dependent Claim 60 words

A sigma-delta analog-to-digital converter comprising: a plurality of loops coupled in cascade, each loop including at least one filter section, wherein each filter section is implemented with multi-sampling circuitry that samples a respective filter input signal at multiple phases of a clock signal; and at least one feed-forward gain element, one gain element coupled between each pair of sequential loops.

Claim 48

Dependent Claim 38 words

The converter of claim 38 wherein said multi-sampling circuitry for each loop includes multiple signal paths, wherein each signal path is clocked by a set of clock signals having clock phases unique from those of other signal paths.

Claim 49

Dependent Claim 24 words

The converter of claim 38 wherein said multi-sampling circuitry for each loop includes two signal paths clocked at alternative phases of the clock signal.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-11-08	2003-05-10	2003-11-09	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-11-08	2007-05-10	2007-11-09	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-11-08	2011-05-10	2011-11-09	$7700.00	Window Closed / Lapsed

Multi-loop Σ Δ analog to digital converter

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