US5574457A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Switched capacitor gain stage
Assignee: NXP USA Inc
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Filing: 1995-06-12
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Granted: 1996-11-12
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Expires: 2015-06-12
Abstract
Abstract A switched capacitor gain stage (21) that samples an input voltage every clock cycle phase for effectively doubling the frequency of operation. The switched capacitor gain stage (21) comprising an amplifier (22), a first capacitor network, and a second capacitor network. Either the first or second capacitor network is sampling an input voltage. For example, the first capacitor network samples an input voltage. Capacitors of the first capacitor network are coupled to sample the input voltage via switches. Capacitors of the second switched capacitor network are coupled around the amplifier (22) in a gain configuration via switches. The capacitors of the second switched capacitor network having a voltage stored from a previous clock phase. In a next clock phase the second switched capacitor network are coupled via switches for sampling an input voltage and the first switched capacitor network is coupled via switches in a gain configuration around the amplifier (22).
Inventors
- 👤 Douglas A. Garrity
- 👤 Patrick L. Rakers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:07
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/44; H03M1/442; H03F; H03F3/00; H03F3/005; H03H; H03H19/00; H03H19/004
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
388 words
A switched capacitor gain stage having an input and an output, the switched capacitor gain stage comprising: an amplifier having an inverting input, a non-inverting input coupled to a power supply terminal, and an output coupled to the output of the switched capacitor gain stage; a first capacitor having a first terminal and a second terminal; a first switch having a first terminal coupled to said first terminal of said first capacitor and a second terminal coupled to said output of said amplifier; a second switch having a first terminal coupled to the input of the switched capacitor gain stage and a second terminal coupled said first terminal of said first capacitor; a third switch having a first terminal coupled to said second terminal of said first capacitor and a second terminal coupled to said inverting input of said amplifier; a fourth switch having a first terminal coupled to said second terminal of said first capacitor and a second terminal coupled to said power supply terminal; a fifth switch having a first terminal coupled to the input of the switched capacitor gain stage and a second terminal; a second capacitor having a first terminal coupled to said second terminal of said fifth switch and a second terminal coupled to said second terminal of said first capacitor; a third capacitor having a first terminal and a second terminal; a sixth switch having a first terminal coupled to said first terminal of said third capacitor and a second terminal coupled to said output of said amplifier; a seventh switch having a first terminal coupled to the input of the switched capacitor gain stage and a second terminal coupled said first terminal of said third capacitor; an eighth switch having a first terminal coupled to said second terminal of said third capacitor and a second terminal coupled to said inverting input of said amplifier; a ninth switch having a first terminal coupled to said second terminal of said third capacitor and a second terminal coupled to said power supply terminal; a tenth switch having a first terminal coupled to the input of the switched capacitor gain stage and a second terminal; and a fourth capacitor having a first terminal coupled to said second terminal of said tenth switch and a second terminal coupled to said second terminal of said third capacitor.
Claim 2
Dependent Claim
388 words
A switched capacitor gain stage having an input and an output, the switched capacitor gain stage comprising: an amplifier having an inverting input, a non-inverting input coupled to a power supply terminal, and an output coupled to the output of the switched capacitor gain stage; a first capacitor having a first terminal and a second terminal; a first switch having a first terminal coupled to said first terminal of said first capacitor and a second terminal coupled to said output of said amplifier; a second switch having a first terminal coupled to the input of the switched capacitor gain stage and a second terminal coupled said first terminal of said first capacitor; a third switch having a first terminal coupled to said second terminal of said first capacitor and a second terminal coupled to said inverting input of said amplifier; a fourth switch having a first terminal coupled to said second terminal of said first capacitor and a second terminal coupled to said power supply terminal; a fifth switch having a first terminal coupled to the input of the switched capacitor gain stage and a second terminal; a second capacitor having a first terminal coupled to said second terminal of said fifth switch and a second terminal coupled to said second terminal of said first capacitor; a third capacitor having a first terminal and a second terminal; a sixth switch having a first terminal coupled to said first terminal of said third capacitor and a second terminal coupled to said output of said amplifier; a seventh switch having a first terminal coupled to the input of the switched capacitor gain stage and a second terminal coupled said first terminal of said third capacitor; an eighth switch having a first terminal coupled to said second terminal of said third capacitor and a second terminal coupled to said inverting input of said amplifier; a ninth switch having a first terminal coupled to said second terminal of said third capacitor and a second terminal coupled to said power supply terminal; a tenth switch having a first terminal coupled to the input of the switched capacitor gain stage and a second terminal; and a fourth capacitor having a first terminal coupled to said second terminal of said tenth switch and a second terminal coupled to said second terminal of said third capacitor.
Claim 3
Dependent Claim
38 words
The switched capacitor gain stage as recited in claim 1 further including an eleventh switch having a first terminal coupled to a first reference input and a second terminal coupled to said first terminal of said second capacitor.
Claim 4
Dependent Claim
38 words
The switched capacitor gain stage as recited in claim 2 further including a twelfth switch having a first terminal coupled to a second reference input and a second terminal coupled to said first terminal of said fourth capacitor.
Claim 5
Dependent Claim
54 words
The switched capacitor gain stage as recited in claim 3 wherein said second, fourth, and fifth switches are closed during a first phase of a clock cycle for sampling a voltage on said first and second capacitors corresponding to a voltage of an applied signal to the input of the switched capacitor gain stage.
Claim 6
Dependent Claim
41 words
The switched capacitor gain stage as recited in claim 4 wherein said first, third, and eleventh switches are closed during a second phase of said clock cycle for placing said first and second capacitors in a gain configuration around said amplifier.
Claim 7
Dependent Claim
42 words
The switched capacitor gain stage as recited in claim 5 wherein said amplifier amplifies said voltage on said first and second capacitors during said second phase of said clock cycle and wherein a reference voltage is applied to said first reference input.
Claim 8
Dependent Claim
54 words
The switched capacitor gain stage as recited in claim 3 wherein said seventh, ninth, and tenth switches are closed during a second phase of a clock cycle for sampling a voltage on said third and fourth capacitors corresponding to said voltage of an applied signal to the input of the switched capacitor gain stage.
Claim 9
Dependent Claim
41 words
The switched capacitor gain stage as recited in claim 7 wherein said sixth, eighth, and twelfth switches are closed during a first phase of said clock cycle for placing said third and fourth capacitors in a gain configuration around said amplifier.
Claim 10
Dependent Claim
43 words
The switched capacitor gain stage as recited in claim 8 wherein said amplifier amplifies a voltage stored on said third and fourth capacitors during a first phase of said clock cycle and wherein a reference voltage is applied to said second reference input.
Claim 11
Dependent Claim
57 words
The switched capacitor gain stage as recited in claim 3 wherein said first and second capacitors, and said third and fourth capacitors are coupled to said amplifier respectively during a second and a first phase of a clock cycle for increasing speed of operation and for maintaining said amplifier in a gain configuration throughout said clock cycle.
Claim 12
Dependent Claim
214 words
A clocked gain stage having an input and an output comprising: an amplifier having an inverting input, a non-inverting input coupled to a power supply terminal, and an output coupled to the output of the clocked gain stage; a first capacitor; a second capacitor, said first and second capacitor being coupled between the input of the clocked gain stage and said power supply terminal during a first phase of a clock cycle for sampling a voltage of an input signal applied to the input of the clocked gain stage and said first and second capacitor being coupled in a gain configuration around said amplifier during a second phase of said clock cycle for amplifying a voltage sampled during said first phase of said clock cycle; a third capacitor; and a fourth capacitor, said third and fourth capacitor being coupled between the input of the clocked gain stage and said power supply terminal during said second phase of said clock cycle for sampling a voltage of said input signal applied to the input of the clocked gain stage and said third and fourth capacitors being coupled in a gain configuration around said amplifier during a first phase of a clock cycle for amplifying a voltage sampled during a second phase of a previous clock cycle.
Claim 13
Dependent Claim
214 words
A clocked gain stage having an input and an output comprising: an amplifier having an inverting input, a non-inverting input coupled to a power supply terminal, and an output coupled to the output of the clocked gain stage; a first capacitor; a second capacitor, said first and second capacitor being coupled between the input of the clocked gain stage and said power supply terminal during a first phase of a clock cycle for sampling a voltage of an input signal applied to the input of the clocked gain stage and said first and second capacitor being coupled in a gain configuration around said amplifier during a second phase of said clock cycle for amplifying a voltage sampled during said first phase of said clock cycle; a third capacitor; and a fourth capacitor, said third and fourth capacitor being coupled between the input of the clocked gain stage and said power supply terminal during said second phase of said clock cycle for sampling a voltage of said input signal applied to the input of the clocked gain stage and said third and fourth capacitors being coupled in a gain configuration around said amplifier during a first phase of a clock cycle for amplifying a voltage sampled during a second phase of a previous clock cycle.
Claim 14
Dependent Claim
40 words
The clocked gain stage as recited in claim 11 wherein either said first and second capacitor or said third and fourth capacitor are coupled around said amplifier for maintaining said amplifier in a gain configuration during an entire clock cycle.
Claim 15
Dependent Claim
59 words
The clocked gain stage as recited in claim 11 wherein said first capacitor is coupled between said inverting input and said output of said amplifier during said second phase of said clock cycle and said second capacitor is coupled between a first reference input and said inverting input of said amplifier during said second phase of said clock cycle.
Claim 16
Dependent Claim
20 words
The clocked gain stage as recited in claim 13 wherein a reference voltage is applied to said first reference input.
Claim 17
Dependent Claim
59 words
The clocked gain stage as recited in claim 11 wherein said third capacitor is coupled between said inverting input and said output of said amplifier during said first phase of said clock cycle and said fourth capacitor is coupled between a second reference input and said inverting input of said amplifier during said first phase of said clock cycle.
Claim 18
Dependent Claim
20 words
The clocked gain stage as recited in claim 15 wherein a reference voltage is applied to said second reference input.
Claim 19
Dependent Claim
60 words
A pipelined Analog to Digital Converter (ADC) including a plurality of series coupled switched capacitor gain stages, the pipelined ADC wherein at least one switched capacitor gain stage of said plurality of series coupled switched capacitor gain stages samples and amplifies a voltage during both clock phases of a clock signal for increasing an operating speed of the pipelined ADC.
Claim 20
Dependent Claim
60 words
A pipelined Analog to Digital Converter (ADC) including a plurality of series coupled switched capacitor gain stages, the pipelined ADC wherein at least one switched capacitor gain stage of said plurality of series coupled switched capacitor gain stages samples and amplifies a voltage during both clock phases of a clock signal for increasing an operating speed of the pipelined ADC.
Claim 21
Dependent Claim
174 words
The pipelined ADC as recited in claim 17 wherein said at least one switched capacitor gain stage includes an input and an output and said at least one switched capacitor gain stage comprises: an amplifier having an inverting input, a non-inverting input coupled to a power supply terminal, and an output; a first capacitor; a second capacitor, said first and second capacitor being coupled between said input of said at least one switched capacitor gain stage and a power supply terminal during a first phase of a clock cycle and said first and second capacitor being coupled in a gain configuration around said amplifier during a second phase of said clock cycle; a third capacitor; and a fourth capacitor, said third and fourth capacitor being coupled between said input of said at least one switched capacitor gain stage and said power supply terminal during said second phase of said clock cycle and said third and fourth capacitors being coupled in a gain configuration around said amplifier during a first phase of a clock cycle.
Claim 22
Dependent Claim
61 words
The pipelined ADC as recited in claim 18 wherein during said second phase of said clock cycle said first capacitor is coupled between said inverting input and said output of said amplifier, said second capacitor is coupled between a first reference input and said inverting input of said amplifier, and a first reference voltage is applied to said first reference input.
Claim 23
Dependent Claim
40 words
The pipelined ADC as recited in claim 19 wherein said first and second capacitors have equal capacitance thereby placing said at least one switched capacitor gain stage in a gain of two during said second phase of said clock cycle.
Claim 24
Dependent Claim
61 words
The pipelined ADC as recited in claim 18 wherein during said first phase of said clock cycle said third capacitor is coupled between said inverting input and said output of said amplifier, said fourth capacitor is coupled between a second reference input and said inverting input of said amplifier, and a second reference voltage is applied to said second reference input.
Claim 25
Dependent Claim
40 words
The pipelined ADC as recited in claim 21 wherein said third and fourth capacitors have equal capacitance thereby placing said at least one switched capacitor gain stage in a gain of two during said first phase of said clock cycle.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-12 | 2000-05-13 | 2000-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-12 | 2004-05-13 | 2004-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-12 | 2008-05-13 | 2008-11-12 | $7700.00 | Window Closed / Lapsed |