Pipelined A/D converter

Claim 2

A pipelined A/D converter for converting an input analog signal to a digital signal with a predetermined conversion rate and producing a conversion output with a predetermined number of bits, said pipelined A/D converter comprising: a plurality of A/D-D/A sub-blocks and one A/D sub-block successively connected in cascade form to determine outputs thereof by several partial bits of the conversion output beginning from the most significant bit; each of said plurality of A/D-D/A sub-blocks comprising a sample-and-hold circuit for successively sampling an input signal fed to said sub-block with a period corresponding to said conversion rate and for holding a resultant value, a sub A/D converter for converting a rod of said sample-and-hold circuit to a digital signal, a latch circuit for latching outputs of said sub A/D converter during an interval of hold mode of said sample-and-hold circuit, a D/A converter for converting outputs of said latch circuit to an analog signal, and a chopper amplifier for sampling a hold output of said sample-and-hold circuit with a delay of half a period as compared with sample timing of said sample-and-hold circuit, amplifying a difference between the sampled value and an output of said D/A converter during a succeeding interval of an amplify mode, and transferring the amplified difference to a sub-block of a succeeding stage as a conversion residue; and said A/D sub-block comprising a sample-and-hold circuit for sampling the conversion residue transferred from the chopper amplifier of the A/D-D/A sub-block of a preceding stage and a sub A/D converter for converting a hold output of said sample-and-hold circuit to a digital signal.

Claim 3

A pipelined A/D converter according to claim 1, wherein each of said plurality of A/D-DA sub-blocks and one A/D sub-block, to which a conversion residue is transferred from a sub-block of a preceding stage, conducts conversion operation on a certain sampled value of said input analog signal with a delay of one period as compared with a sub-block of a preceding stage.

Claim 4

A pipelined A/D converter for converting an input analog signal to a digital signal with a predetermined conversion rate and producing a conversion output with a predetermined number of bits, said pipelined A/D converter comprising: an input sample-and-hold circuit for successively sampling said input analog signal with a period corresponding to said conversion rate and holding a resultant value; a plurality of A/D-D/A sub-blocks and one A/D sub-block successively connected in cascade form so as to follow said input sample-and-hold circuit to determine outputs thereof by several partial bits of the conversion output beginning from the most significant bit; each of said plurality of A/D-D/A sub-blocks comprising a sample-and-hold circuit for successively sampling an input signal fed to said sub-block with a period corresponding to said conversion rate and for holding a resultant value, a sub A/D converter for converting the input signal fed to said sub-block to a digital signal, a latch circuit for latching outputs of said sub A/D converter, a D/A converter for converting outputs of said latch circuit to an analog signal, and a chopper amplifier for sampling a hold output of said sample-and-hold circuit with a delay of half a period as compared with sample timing of said sample-and-hold circuit, amplifying a difference between the sampled value and an output of said D/A converter during a succeeding interval of amplify mode, and transferring the amplified difference to a sub-block of a succeeding stage as a conversion residue; and said A/D sub-block comprising a sub A/D converter for converting the conversion residue transferred from the chopper amplifier of the A/D-D/A sub-block of a preceding stage to a digital signal.

Claim 5

A pipelined A/D converter for converting an input analog signal to a digital signal with a predetermined conversion rate and producing a conversion output with a predetermined number of bits, said pipelined A/D converter comprising: an input sample-and-hold circuit for successively sampling said input analog signal with a period corresponding to said conversion rate and holding a resultant value; a plurality of A/D-D/A sub-blocks and one A/D sub-block successively connected in cascade form so as to follow said input sample-and-hold circuit to determine outputs thereof by several partial bits of the conversion output beginning from the most significant bit; each of said plurality of A/D-D/A sub-blocks comprising a sample-and-hold circuit for successively sampling an input signal fed to said sub-block with a period corresponding to said conversion rate and for holding a resultant value, a sub A/D converter for converting the input signal fed to said sub-block to a digital signal, a latch circuit for latching outputs of said sub A/D converter, a D/A converter for converting outputs of said latch circuit to an analog signal, and a chopper amplifier for sampling a hold output of said sample-and-hold circuit with a delay of half a period as compared with sample timing of said sample-and-hold circuit, amplifying a difference between the sampled value and an output of said D/A converter during a succeeding interval of amplify mode, and transferring the amplified difference to a sub-block of a succeeding stage as a conversion residue; and said A/D sub-block comprising a sub A/D converter for converting the conversion residue transferred from the chopper amplifier of the A/D-D/A sub-block of a preceding stage to a digital signal.

Claim 6

A pipelined A/D converter according to claim 3, wherein each of said plurality of A/D-D/A sub-blocks and one A/D sub-block, to which a conversion residue is transferred from a sub-block of a preceding stage, conducts conversion operation on a certain sampled value of said input analog signal with a delay of one period as compared with a sub-block of a preceding stage.

Claim 7

A pipelined A/D converter according to claim 3, wherein a chopper amplifier in each of said plurality of A/D-D/A sub-blocks conducts sample operation with a delay of one period as compared with a chopper amplifier in an A/D-D/A sub-block of a preceding stage or said input sample-and-hold circuit of a preceding stage.

Claim 8

A pipelined A/D converter for converting an input analog signal to a digital signal with a predetermined conversion rate and producing a conversion output with a predetermined number of bits, said pipelined A/D converter comprising: a plurality of A/D-D/A sub-blocks and one A/D sub-block successively connected in cascade form to determine outputs thereof by several partial bits of the conversion output beginning from the most significant bit; each of said plurality of A/D-D/A sub-blocks comprising a first sample-and-hold circuit for successively sampling an input signal fed to said sub-block with a period corresponding to said conversion rate and for holding a resultant value, a sub A/D converter for converting a hold output of said first sample-and-hold circuit to a digital signal, a latch circuit for latching outputs of said sub A/D converter during an interval of hold mode of said first sample-and-hold circuit, a D/A converter for converting outputs of said latch circuit to an analog signal, a second sample-and-hold circuit for sampling the hold output of said first sample-and-hold circuit with a delay of half a period as compared with sample timing of said first sample-and-hold circuit, and a chopper amplifier for sampling a hold output of said second sample-and-hold circuit with a further delay of half a period as compared with sample timing of said second sample-and-hold circuit, amplifying a difference between the sampled value and an output of said D/A converter during a succeeding interval of amplify mode, and transferring the amplified difference to a sub-block of a succeeding stage as a conversion residue; and said A/D sub-block comprising a sample-and-hold circuit for sampling the conversion residue transferred from the chopper amplifier of the A/D-D/A sub-bock of a preceding stage and a sub A/D converter for converting a hold output of said sample-and-hold circuit to a digital signal.

Claim 9

A pipelined A/D converter for converting an input analog signal to a digital signal with a predetermined conversion rate and producing a conversion output with a predetermined number of bits, said pipelined A/D converter comprising: a plurality of A/D-D/A sub-blocks and one A/D sub-block successively connected in cascade form to determine outputs thereof by several partial bits of the conversion output beginning from the most significant bit; each of said plurality of A/D-D/A sub-blocks comprising a first sample-and-hold circuit for successively sampling an input signal fed to said sub-block with a period corresponding to said conversion rate and for holding a resultant value, a sub A/D converter for converting a hold output of said first sample-and-hold circuit to a digital signal, a latch circuit for latching outputs of said sub A/D converter during an interval of hold mode of said first sample-and-hold circuit, a D/A converter for converting outputs of said latch circuit to an analog signal, a second sample-and-hold circuit for sampling the hold output of said first sample-and-hold circuit with a delay of half a period as compared with sample timing of said first sample-and-hold circuit, and a chopper amplifier for sampling a hold output of said second sample-and-hold circuit with a further delay of half a period as compared with sample timing of said second sample-and-hold circuit, amplifying a difference between the sampled value and an output of said D/A converter during a succeeding interval of amplify mode, and transferring the amplified difference to a sub-block of a succeeding stage as a conversion residue; and said A/D sub-block comprising a sample-and-hold circuit for sampling the conversion residue transferred from the chopper amplifier of the A/D-D/A sub-bock of a preceding stage and a sub A/D converter for converting a hold output of said sample-and-hold circuit to a digital signal.

Claim 10

A pipelined A/D converter according to claim 6, wherein each of said plurality of A/D-D/A sub-blocks and one A/D sub-block, to which a conversion residue is transferred from a sub-block of a preceding stage, conducts conversion operation on a certain sampled value of said input analog signal with a delay of 1.5 periods as compared with a sub-block of a preceding stage.