US3820112A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed analog-to-digital conversion system
Assignee: Individual
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Filing: 1973-10-01
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Granted: 1974-06-25
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Expires: 1993-10-01
Abstract
Abstract A high speed analog-to-digital conversion system is provided by utilizing a number of standard analog-to-digital converters in a ''''pipeline'''' mode of operation, sampling the analog data at high speeds, multiplexing each sample successively into each channel of the analog-to-digital converter array, performing the serial analog-to-digital conversion in each channel, feeding the serial data from each channel into its respective tri-state shift register, and finally reading the contents of each shift register in parallel to a common bus.
Inventors
- 👤 A Roth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:33
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
71 words
A high speed analog-to-digital conveRsion system comprising: a. an input source of analog voltage, b. a plurality of parallel connected conversion channels coupled to said input source, c. clock control circuit means coupled to each of said conversion channels for controlling the sampling and conversion of said analog voltage in a predetermined sequence so that the time of conversion is the product of the sampling period times the number of channels.
Claim 2
Dependent Claim
71 words
A high speed analog-to-digital conveRsion system comprising: a. an input source of analog voltage, b. a plurality of parallel connected conversion channels coupled to said input source, c. clock control circuit means coupled to each of said conversion channels for controlling the sampling and conversion of said analog voltage in a predetermined sequence so that the time of conversion is the product of the sampling period times the number of channels.
Claim 3
Dependent Claim
23 words
The conversion system of claim 1 wherein each of said conversion channels includes an analog-to-digital converter connected in a pipeline mode of operation.
Claim 4
Dependent Claim
126 words
The conversion system of claim 1 wherein each of said conversion channels includes: a. switch sampling means coupled to said analog voltage source for sampling said analog voltage in response to a control signal from said clock control circuit means, b. sample and hold circuit means coupled to said switch sampling means for holding the sampled voltage for a predetermined time, c. converter circuit means coupled to said hold circuit means for converting said sampled voltage to a digital equivalent, d. shift register means coupled to said converter circuit means for storing the output of said converter circuit, e. output terminal means coupled to said shift register means for receiving the output of said register in response to a reading signal from said converter circuit means.
Claim 5
Dependent Claim
26 words
The system of claim 3 wherein said sample and hold circuit means holds the sampled voltage until all channels in sequence have sampled the analog voltage.
Claim 6
Dependent Claim
30 words
The system of claim 3 wherein the number of bits in each converter channel may be different from the total number of channels required for a desired speed of conversion.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-24 | 1977-12-24 | 1978-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-24 | 1981-12-24 | 1982-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-24 | 1985-12-24 | 1986-06-25 | $7700.00 | Window Closed / Lapsed |