Abstract An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier. Alternatively, improved transistors for electrostatic discharge protection can be formed in the silicon film by fabricating the transistor in a plurality of electrically isolated segments, each segment having source and drain regions separated by a channel region with the regions being electrically interconnected with like regions in other segments. Increased ESD current can be realized as compared to the ESD current for a wider unsegmented device.
A silicon-on-insulator field effect transistor for use in an electrostatic discharge protection circuit comprising an insulating layer, a semiconductor material layer on said insulating layer, a plurality of phsically and electrically isolated regions of semiconductor material formed from said semiconductor material region, each isolated region having a source region spaced from a drain region by a channel region, a first interconnect means for electrically connecting all of said source regions, a second interconnect means for electrically connecting all of said drain regions, and a third interconnect means overlying all of said channel regions and functioning as a common gate.
Claim 2
Dependent Claim
99 words
A silicon-on-insulator field effect transistor for use in an electrostatic discharge protection circuit comprising an insulating layer, a semiconductor material layer on said insulating layer, a plurality of phsically and electrically isolated regions of semiconductor material formed from said semiconductor material region, each isolated region having a source region spaced from a drain region by a channel region, a first interconnect means for electrically connecting all of said source regions, a second interconnect means for electrically connecting all of said drain regions, and a third interconnect means overlying all of said channel regions and functioning as a common gate.
Claim 3
Dependent Claim
22 words
The silicon-on-insulator field effect transistor as defined by claim 1 wherein said plurality of electrically isolated regions comprise physically isolated mesa structures.