Patent US5976973A successfully refreshed from Google Patents.
US5976973A
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Method of making a semiconductor device having planarized insulating layer
Assignee: Fujitsu Ltd
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Filing: 1997-10-10
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Granted: 1999-11-02
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Expires: 2017-10-10
Abstract
Abstract A method of manufacturing a semiconductor device has the steps of: forming a wiring pattern by dry etching a wiring layer on a semiconductor substrate, using a resist pattern as a mask; immersing the wiring pattern in amine containing liquid to remove deposition residues formed during the dry etching; then, processing the wiring pattern with fluid not containing amine and being capable of removing deposition residues; forming a conformal insulating layer on the processed wiring pattern; and forming an insulating layer having a planarizing function on the conformal insulating layer by CVD. This method is suitable for multi-layer wiring, and can form an interlayer insulating film having a satisfactory planarizing function.
Inventors
- 👤 Koichiro Ohira
- 👤 Katsuyuki Karakawa
- 👤 Kazutoshi Izumi
- 👤 Masahiko Doki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:51
CPC Classifications
H; H10; H10P; H10P70/00; H10P70/20; H10P70/27; H10P70/273; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/66; H10P14/662; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/6922; H10P14/6923; H10P14/6924; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/71; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; H10P14/6336; H10P95/00; H10P95/06; Y; Y10; Y10S; Y10S438/00; Y10S438/906
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
108 words
A method of manufacturing a semiconductor device comprising the steps of: forming a wiring layer on a semiconductor substrate; forming a wiring pattern by dry etching the wiring layer using a resist pattern as a mask; immersing the wiring pattern in amine containing liquid to remove deposition residues formed during the dry etching; processing the wiring pattern having been immersed in the amine containing liquid with fluid not containing amine and containing ions or radicals which are capable of removing deposition residues; forming a conformal insulating layer on the processed wiring pattern; and forming an insulating layer having a planarizing function on the conformal insulating layer by CVD.
Claim 2
Independent Claim
108 words
A method of manufacturing a semiconductor device comprising the steps of: forming a wiring layer on a semiconductor substrate; forming a wiring pattern by dry etching the wiring layer using a resist pattern as a mask; immersing the wiring pattern in amine containing liquid to remove deposition residues formed during the dry etching; processing the wiring pattern having been immersed in the amine containing liquid with fluid not containing amine and containing ions or radicals which are capable of removing deposition residues; forming a conformal insulating layer on the processed wiring pattern; and forming an insulating layer having a planarizing function on the conformal insulating layer by CVD.
Claim 3
Dependent Claim
30 words
A method according to claim 1, wherein said step of forming the insulating film having the planarizing function includes the step of forming an insulating film by atmospheric pressure CVD.
Claim 4
Dependent Claim
22 words
A method according to claim 1, wherein the wiring layer comprises lamination of a barrier metal layer and a main wiring layer.
Claim 5
Dependent Claim
18 words
A method according to claim 3, wherein the wiring layer comprises an antireflection film laminated on the lamination.
Claim 6
Dependent Claim
31 words
A method according to claim 3, wherein the barrier metal layer is a TiN layer or a lamination of a Ti layer and a TiN layer formed on the Ti layer.
Claim 7
Dependent Claim
41 words
A method according to claim 3, wherein said main wiring layer includes one of a W layer, an Al--Cu alloy layer, an Al--Cu--Si alloy layer, and a lamination of a Cu layer and a TiN layer formed on the Cu layer.
Claim 8
Dependent Claim
19 words
A method according to claim 1, wherein the amine containing liquid contains one of primary, secondary and tertiary amines.
Claim 9
Dependent Claim
32 words
A method according to claim 1, wherein said step of processing the wiring pattern with fluid includes the step of immersing the wiring pattern in liquid which contains fluorine compound or choline.
Claim 10
Dependent Claim
26 words
A method according to claim 1, wherein said step of processing the wiring pattern with fluid includes the step of exposing the substrate in oxygen plasma.
Claim 11
Dependent Claim
60 words
A method according to claim 1, wherein the conformal insulating layer is lamination of a first layer and a second layer formed on the first layer, the first layer is denser than the second layer, and the second layer has a nature more excellent than the first layer as an underlying layer of the insulating film having the planarizing function.
Claim 12
Dependent Claim
69 words
A method according to claim 10, wherein the compositions of the first layer contain Si 25 at %-45 at %, O 30 at %-65 at %, N 0 at %-25 at %, H 0.01 at %-25 at %, Ar 0.001 at %-3 at %, F 0.001 at %-25 at %, B 0.001 at %-10 at %, P 0.001 at %-10 at %, and C 0.001 at %-50 at %.
Claim 13
Dependent Claim
92 words
A method according to claim 10, the compositions of the second layer contain Si 25 at %-35 at % or Si 45 at %-55 at %, O 45 at %-70 at % or O 5 at %-25 at %, N 0.0001 at %-3.0 at %, or N 15 at %-30 at %, H 0.0001 at %-5 at % or H 10.0 at %-25 at %, respectively, and Ar 0.0001 at %-3 at %, F 0.0001 at %-15 at %, P 0.0001 at %-10 at %, and C 0.0001 at %-2 at %.
Claim 14
Dependent Claim
154 words
A method according to claim 1, wherein first source gas used in said step of forming the conformal insulating film is one or a combination of two to five materials selected from the group consisting of SiH 4 , Si 2 H 6 , Si(OC--R) 4 , HSi(OC--R) 3 , SiF 4 , SiH 2 F 2 , C 2 F 6 , FSi(OC--R) 3 , F 2 Si(OC--R) 2 , R--PH 2 , R 2 --PH, B 2 H 6 , P(O--R) 3 , PO(O--R) 3 R 3 --B, R 2 --BH, R--BH 2 , B(O--R) 3 , BF 3 , FB(O--R) 2 , F 2 B(O--R), where R is alcoxyl, and second source gas is one or a combination of two to five materials selected from the group consisting of N 2 O, O 2 , O 3 , O, F 2 , NH 3 , rare gases, and N 2 .
Claim 15
Dependent Claim
73 words
A method according to claim 1, wherein the compositions of the insulating film having the planarizing function contain Si 25 at %-45 at %, O 30 at %-65 at %, N 0.001 at %-25 at %, H 0.001 at %-25 at %, Ar 0.001 at %-3 at %, F 0.001 at %-25 at %, B 0.001 at %-10 at %, P 0.001 at %-10 at %, and C 0.001 at %-50 at %.
Claim 16
Dependent Claim
149 words
A method according to claim 14, wherein first source gas used in said step of forming the insulating film having the planarizing function is one or a combination of two or three materials selected from the group consisting of SiH 4 , Si 2 H 6 , Si(OC--R) 4 , HSi(OC--R) 3 , SiF 4 , SiH 2 F 2 , C 2 F 6 , FSi(OC--R) 3 , F 2 Si(OC--R) 2 , R--PH 2 , R 2 --PH, B 2 H 6 , P(O--R) 3 , PO(O--R) 3 --R 3 --B, R 2 --BH, R--BH 2 , B(O--R) 3 , BF 3 , FB(O--R) 2 , F 2 B(O--R), where R is alcoxyl, and second source gas used is one or a combination of two or three materials selected from the group consisting of O 2 , O 3 , O, rare gas, and N 2 .
Claim 17
Independent Claim
123 words
A method of manufacturing a semiconductor device comprising the steps of: forming a wiring layer on a semiconductor substrate; forming a wiring pattern by dry etching the wiring layer using a resist pattern as a mask; immersing the wiring pattern in amine containing liquid to remove deposition residues formed during the dry etching; processing the wiring pattern having been immersed in the amine containing liquid with fluid containing at least one from the group consisting of fluoride ion, hydroxide ion, oxygen radical, oxygen ion, and choline but not containing amine and being capable of removing deposition residues; forming a conformal insulating layer on the processed wiring pattern; and forming an insulating layer having a planarizing function on the conformal insulating layer by CVD.
Claim 18
Independent Claim
123 words
A method of manufacturing a semiconductor device comprising the steps of: forming a wiring layer on a semiconductor substrate; forming a wiring pattern by dry etching the wiring layer using a resist pattern as a mask; immersing the wiring pattern in amine containing liquid to remove deposition residues formed during the dry etching; processing the wiring pattern having been immersed in the amine containing liquid with fluid containing at least one from the group consisting of fluoride ion, hydroxide ion, oxygen radical, oxygen ion, and choline but not containing amine and being capable of removing deposition residues; forming a conformal insulating layer on the processed wiring pattern; and forming an insulating layer having a planarizing function on the conformal insulating layer by CVD.
Claim 19
Independent Claim
118 words
A method of manufacturing a semiconductor device comprising the steps of: forming a wiring layer on a semiconductor substrate, the wiring layer comprising lamination of a barrier metal layer and a main wiring layer; forming a wiring pattern by dry etching the wiring layer using a resist pattern as a mask; immersing the wiring pattern in amine containing liquid to remove deposition residues formed during the dry etching; processing the wiring pattern having been immersed in the amine containing liquid with fluid not containing amine and being capable of removing deposition residues; forming a conformal insulating layer on the processed wiring pattern; and forming an insulating layer having a planarizing function on the conformal insulating layer by CVD.
Claim 20
Independent Claim
118 words
A method of manufacturing a semiconductor device comprising the steps of: forming a wiring layer on a semiconductor substrate, the wiring layer comprising lamination of a barrier metal layer and a main wiring layer; forming a wiring pattern by dry etching the wiring layer using a resist pattern as a mask; immersing the wiring pattern in amine containing liquid to remove deposition residues formed during the dry etching; processing the wiring pattern having been immersed in the amine containing liquid with fluid not containing amine and being capable of removing deposition residues; forming a conformal insulating layer on the processed wiring pattern; and forming an insulating layer having a planarizing function on the conformal insulating layer by CVD.
Claim 21
Dependent Claim
18 words
A method according to claim 17, wherein the wiring layer comprises an antireflection film laminated on the lamination.
Claim 22
Dependent Claim
31 words
A method according to claim 17, wherein the barrier metal layer is a TiN layer or a lamination of a Ti layer and a TiN layer formed on the Ti layer.
Claim 23
Dependent Claim
41 words
A method according to claim 17, wherein said main wiring layer includes one of a W layer, an Al--Cu alloy layer, an Al--Cu--Si alloy layer, and a lamination of a Cu layer and a TiN layer formed on the Cu layer.
Claim 24
Independent Claim
121 words
A method of manufacturing a semiconductor device comprising the steps of: forming a wiring layer on a semiconductor substrate; forming a wiring pattern by dry etching the wiring layer using a resist pattern as a mask; immersing the wiring pattern in amine containing liquid to remove deposition residues formed during the dry etching; processing the wiring pattern having been immersed in the amine containing liquid with fluid not containing amine and being capable of removing deposition residues, said processing including a step of immersing the wiring pattern in liquid which contains fluorine compound or choline; forming a conformal insulating layer on the processed wiring pattern; and forming an insulating layer having a planarizing function on the conformal insulating layer by CVD.
Claim 25
Independent Claim
121 words
A method of manufacturing a semiconductor device comprising the steps of: forming a wiring layer on a semiconductor substrate; forming a wiring pattern by dry etching the wiring layer using a resist pattern as a mask; immersing the wiring pattern in amine containing liquid to remove deposition residues formed during the dry etching; processing the wiring pattern having been immersed in the amine containing liquid with fluid not containing amine and being capable of removing deposition residues, said processing including a step of immersing the wiring pattern in liquid which contains fluorine compound or choline; forming a conformal insulating layer on the processed wiring pattern; and forming an insulating layer having a planarizing function on the conformal insulating layer by CVD.
Claim 26
Independent Claim
115 words
A method of manufacturing a semiconductor device comprising the steps of: forming a wiring layer on a semiconductor substrate; forming a wiring pattern by dry etching the wiring layer using a resist pattern as a mask; immersing the wiring pattern in amine containing liquid to remove deposition residues formed during the dry etching; processing the wiring pattern having been immersed in the amine containing liquid with fluid not containing amine and being capable of removing deposition residues, said processing including a step of exposing the substrate in oxygen plasma; forming a conformal insulating layer on the processed wiring pattern; and forming an insulating layer having a planarizing function on the conformal insulating layer by CVD.
Claim 27
Independent Claim
115 words
A method of manufacturing a semiconductor device comprising the steps of: forming a wiring layer on a semiconductor substrate; forming a wiring pattern by dry etching the wiring layer using a resist pattern as a mask; immersing the wiring pattern in amine containing liquid to remove deposition residues formed during the dry etching; processing the wiring pattern having been immersed in the amine containing liquid with fluid not containing amine and being capable of removing deposition residues, said processing including a step of exposing the substrate in oxygen plasma; forming a conformal insulating layer on the processed wiring pattern; and forming an insulating layer having a planarizing function on the conformal insulating layer by CVD.
References Cited (Backward Citations)
US4770899A
Cited
JPH07201794A
Cited
US5630904A
Cited
US5744402A
Cited
US5759973A
Cited
US5849639A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-01 | 2003-05-03 | 2003-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-01 | 2007-05-03 | 2007-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-01 | 2011-05-03 | 2011-11-02 | $7700.00 | Window Closed / Lapsed |