Universal serial bus device controller comprising a FIFO associated with a plurality of endpoints and a memory for storing an identifier of a current endpoint

Claim 2

A controller for operating a peripheral in accordance with the Universal Serial Bus (USB) specification, comprising: means for receiving data packets; a FIFO for storing data contained in received data packets, said FIFO being associated with at least two endpoints; a packet control store for storing, as a current endpoint, an identifier contained in an endpoint field of a received data packet, wherein data stored in said FIFO corresponds to said current endpoint; a state machine to control sequencing of a transaction based on said current endpoint, said transaction including reception and transmission of a plurality of data packets, said state machine thereby being capable of controlling sequencing of transactions with any endpoint; a plurality of endpoint control stores; and a selector coupled to said plurality of endpoint control stores for selecting one of said endpoint control stores based on said current endpoint; said state machine coupled to receive the contents of a selected one of said endpoint control stores.

Claim 3

The controller of claim 1 further including means for transmitting data packets, coupled to said FIFO for transmission of data from said device.

Claim 4

The controller of claim 2 wherein said endpoint control stores include a bus turnaround delay specifier, said means for transmitting data coupled to receive the bus turnaround delay specifier of said selected endpoint control store.

Claim 5

The controller of claim 1 further including a port for attachment to a host; said port including means for simulating the disconnection and connection of a universal serial bus device.

Claim 6

The controller of claim 4 wherein said port comprises a D+ signal line and a D- signal line and a pull-up resistor coupled to one of said signal lines, said means for simulating includes a first transistor switch coupled to pull said D+ and D- signal lines to a voltage in the range of 2.0 to 0.8 volts and a second transistor switch coupled to disconnect said pull-up resistor.

Claim 7

A controller for transmitting data in accordance with the Universal Serial Bus (USB) specification, comprising: a microcontroller interface for connection to a microcontroller; a port for attachment to a USB host; serial means, coupled to said port, for receiving and transmitting USB packets, including means for extracting an endpoint identifier from a packet of a TOKEN type; control means for managing the transfer of packets between said USB host and said microcontroller, including first memory means for storing an extracted endpoint identifier, thereby defining an active endpoint; a FIFO for storing data obtained from a received packet, said FIFO associated with said active endpoint; state machine means, coupled to said control means, for controlling the sequencing of a transaction with said USB host based on said active endpoint, said transaction comprising plural packets; and a second memory means for storing configuration and state information for each endpoint; said state machine means coupled to said second memory means to receive configuration and state information corresponding to said active endpoint.

Claim 8

A controller for transmitting data in accordance with the Universal Serial Bus (USB) specification, comprising: a microcontroller interface for connection to a microcontroller; a port for attachment to a USB host; serial means, coupled to said port, for receiving and transmitting USB packets, including means for extracting an endpoint identifier from a packet of a TOKEN type; control means for managing the transfer of packets between said USB host and said microcontroller, including first memory means for storing an extracted endpoint identifier, thereby defining an active endpoint; a FIFO for storing data obtained from a received packet, said FIFO associated with said active endpoint; state machine means, coupled to said control means, for controlling the sequencing of a transaction with said USB host based on said active endpoint, said transaction comprising plural packets; and a second memory means for storing configuration and state information for each endpoint; said state machine means coupled to said second memory means to receive configuration and state information corresponding to said active endpoint.

Claim 9

The controller of claim 6 wherein said second memory means includes a bus turnaround time specifier for each endpoint, said serial means coupled to receive the bus turnaround time specifier corresponding to said active endpoint.

Claim 10

The controller of claim 6 further including means for generating an interrupt during the reception of a packet of a TOKEN type, thereby signaling said microcontroller to prepare for storing data to or reading data from said FIFO.

Claim 11

The controller of claim 8 wherein said means for generating an interrupt is characterized by producing an interrupt prior to reception of the EOP delimiter of a TOKEN-type of packet.

Claim 12

The controller of claim 8 wherein said means for generating an interrupt is characterized by producing an interrupt during reception of the CRC portion of a TOKEN-type of packet.

Claim 13

The controller of claim 6 further including means for simulating a disconnection from a USB host and a subsequent reconnection to said USB host.

Claim 14

The controller of claim 11 wherein said port includes a D+ signal line, a D- signal line, and a pull-up resistor coupled to one of said signal lines, and wherein said means for simulating includes a first transistor switch coupled to momentarily pull the potential of said D+ and D- lines in the range of 2.0 to 0.8 volts and a second transistor switch coupled to disconnect said pull-up resistor, thereby creating a single-ended zero (SE0) condition.

Claim 15

The controller of claim 6 further including a second FIFO wherein each of said FIFO's is associated with a plurality of endpoints; the controller further including means for storing data into one of said FIFO's depending upon the endpoint identified by said active endpoint.

Claim 18

The method of claim 14 wherein said step of receiving said second packet includes receiving a SYNC, a packet id, a device address, an endpoint address, a CRC, and an EOP delimiter, and said step of reading out said first data is initiated prior to receiving said EOP delimiter.

Claim 19

The method of claim 14 wherein said step of receiving said second packet includes receiving a SYNC, a packet id, a device address, an endpoint address, a CRC, and an EOP delimiter, and said step of reading out said first data is initiated during reception of said CRC.

Claim 20

The method of claim 14 further including: receiving a fifth packet, said fifth packet containing a third endpoint identifier; storing said third endpoint identifier thereby redefining said current endpoint; receiving a sixth packet corresponding to said current endpoint, said sixth packet containing third data; storing said third data into a second FIFO; and reading out said third data from said second FIFO.

Claim 23

The method of claim 18 wherein said step of receiving said first packet includes receiving a SYNC, a packet id, a device address, an endpoint address, a CRC, and an EOP delimiter, and said step of storing data is initiated prior to receiving said EOP delimiter.

Claim 24

The method of claim 18 wherein said step of receiving said first packet includes receiving a SYNC, a packet id, a device address, an endpoint address, a CRC, and an EOP delimiter, and said step of storing data is initiated during reception of said CRC.

Claim 25

The method of claim 18 further including: associating a first plurality of endpoints with said first FIFO; associating a second plurality of endpoints with a second FIFO; and prior to said step of storing data, determining whether the endpoint of said selected data is associated with said first FIFO and if the endpoint of said selected data is associated with said second FIFO, then storing said selected data into said second FIFO.

Claim 28

The method of claim 22 wherein said first packet is an IN-type packet.

Claim 29

The method of claim 22 wherein said step of storing data contained in said second packet is initiated during reception of said second packet and prior to receiving an EOP delimiter of said second packet.

Claim 30

The method of claim 24 further including: generating data to be sent to a host; receiving a third packet, said third packet containing a second endpoint identifier; storing said second endpoint as said current endpoint; matching said current endpoint to one of said first and second FIFO's; storing generated data into a matched one of said FIFO's; and transmitting data from said FIFO to said host.

Claim 31

The method of claim 25 wherein said third packet is an OUT-type packet.

Claim 32

The method of claim 25 wherein said step of storing generated data is initiated during reception of said third packet and prior to receiving an EOP delimiter of said third packet.