Shared buffer switching module

Claim 2

A buffered communication switch for switching data cells between input ports and selected output ports, comprising: one or more input ports for receiving incoming data cells; a plurality of output ports; a shared buffer memory for storing data cells received via said one or more input ports while awaiting transmission via one or more of said output ports; a common bus interconnecting said input ports, said output ports, and said shared buffer memory; means for examining said incoming data cells to select one or more of said output ports appropriate for transmission of the cell; means for selecting a vacant address in said shared buffer memory for storing one of said incoming data cells; means for storing said one of said incoming data cells to provide a stored data cell at said vacant address and for storing the address thereof at one or more of said output ports selected for transmission of said stored data cell; means for retrieving said stored data cell when time is available for transmission thereof via said selected one or more output ports; and wherein the transfer of an incoming data cell from said input ports to said shared buffer memory is interleaved via said common bus with the transfer of data cells from said shared buffer memory to said output ports.

Claim 3

A buffered communication switch according to claim 1 wherein said means for selecting a vacant address includes means for maintaining a linked list of vacant addresses; means, coupled to said means for storage, for removing an address from said linked list when assigned for storage of a data cell; and means, coupled to said means for retrieving, for adding an address to said linked list when the data cell stored at the address has been transmitted from all selected ports for said data cell.

Claim 4

A buffered communication switch according to claim 1 wherein said means for selecting a vacant address includes a memory map maintained to indicate currently assigned exit ports for stored data cells; and a content addressable memory means using parallel flow through logic to determine a vacant address and for storing said incoming data cell at said vacant address in said shared buffer memory.

Claim 5

A buffered communication switch according to claim 1 wherein said means for examining incoming data cells includes a translator for examining the header of said incoming data cell to determine the output port or ports and the cell priority.

Claim 6

A buffered communication switch according to claim 4 for routing data cells according to virtual path and circuit designations in the data cell wherein said translator operates on a data compressed format according to the number of virtual paths and circuits being serviced.

Claim 7

A buffered communication switch according to claim 1 wherein said means for examining incoming data cells includes a translator for examining and translating the header of said incoming data cell and wherein other data cells are being transferred to and from said shared memory on a word-by-word basis while translations are being carried out.

Claim 8

A buffered communication switch according to claim 6 further including means for transmitting said data cell from one or more of said output ports when time is available; and translator means for examining the header of each outgoing data cell and changing said header according to the outgoing transmission link.

Claim 9

A buffered communication switch according to claim 1 wherein said means for storing and said means for retrieving operate on a word-by-word interleaved basis.

Claim 10

A buffered communication switch for the priority switching of data cells between input ports and selected output ports, said data cells each having a data cell priority, comprising: one or more input ports for receiving incoming data cells; a plurality of output ports each including a plurality of priority address queues associated therewith; a shared buffer memory for storing said incoming data cells received via said one or more input ports while awaiting transmission via one or more of said output ports; a translator for examining said incoming data cells to determine the data cell priority, and to select one or more of said output ports for subsequent transmission of said incoming data cells; an address selector for selecting a vacant address in said shared buffer memory for storing an incoming data cell; means for storing said incoming data cell to provide a stored data cell at said vacant address determined by said address selector and for storing said vacant address in a selected priority queue at said one or more output ports selected by said translator for subsequent transmission of said stored data cell; and means for retrieving coupled to said shared memory to receive said stored data cell at said address in said shared memory for transmission of said stored data cell via said selected output port when said address is at the head of the highest occupied priority queue at said selected port.

Claim 11

A buffered communication switch for the priority switching of data cells between input ports and selected output ports, said data cells each having a data cell priority, comprising: one or more input ports for receiving incoming data cells; a plurality of output ports each including a plurality of priority address queues associated therewith; a shared buffer memory for storing said incoming data cells received via said one or more input ports while awaiting transmission via one or more of said output ports; a translator for examining said incoming data cells to determine the data cell priority, and to select one or more of said output ports for subsequent transmission of said incoming data cells; an address selector for selecting a vacant address in said shared buffer memory for storing an incoming data cell; means for storing said incoming data cell to provide a stored data cell at said vacant address determined by said address selector and for storing said vacant address in a selected priority queue at said one or more output ports selected by said translator for subsequent transmission of said stored data cell; and means for retrieving coupled to said shared memory to receive said stored data cell at said address in said shared memory for transmission of said stored data cell via said selected output port when said address is at the head of the highest occupied priority queue at said selected port.

Claim 12

A buffered communication switch according to claim 9 wherein said address selector for selecting a vacant address includes means for maintaining a linked list of vacant addresses; means, coupled to said means for storage, for removing an address from said linked list when assigned for storage of a data cell; and means, coupled to said means for retrieving, for adding an address to said linked list when the data cell stored at the address has been transmitted from all selected ports for said data cell.

Claim 13

A buffered communication switch according to claim 9 wherein said address selector for selecting a vacant address includes a memory map maintained to indicate currently assigned output ports for stored data cells; and a content addressable memory means using parallel flow through logic to determine a vacant address and for storing said incoming data cell at said vacant address in said shared buffer memory.

Claim 14

A buffered communication switch according to claim 9 for routing data cells according to virtual path and circuit designations in the data cell wherein said translator operates on a data compressed format according to the number of virtual paths and circuits being serviced.

Claim 15

A buffered communication switch according to claim 9 wherein said translator examines and translates the header of said incoming data cell and wherein other data cells are being transferred to and from said shared memory on a word-by-word basis while translations are being carried out.

Claim 16

A buffered communication switch according to claim 13 further including means for transmitting said data cell from one or more of said output ports when time is available; and further translator means for examining the header of each outgoing data cell and changing said header according to the outgoing transmission link.

Claim 17

A buffered communication switch according to claim 9 wherein said means for storing and said means for retrieving operate on a word-by-word interleaved basis.

Claim 18

A buffered communication switch for switching multi-word data cells between input ports and selected output ports, comprising: a plurality of input ports for receiving incoming data cells; a plurality of output ports; a shared buffer memory for storing said incoming data cells received via said input ports while awaiting transmission via one or more of said output ports; a translator for examining said incoming data cells to designate one or more of said output ports for transmission of said incoming data cells; an address selector for selecting a vacant address in said shared buffer memory for storing an incoming data cell; means for storing said incoming data cell at said vacant address to provide a stored data cell and for storing the address thereof at said one or more output ports selected for transmission of said stored data cell; and means for retrieving coupled to said shared memory to receive said stored data cell at said address in said shared memory when time is available for transmission of said data cell via said selected one or more output ports; said means for storing and said means for retrieving being operable to transfer data cells to and from said shared buffer memory on a word-by-word basis.

Claim 19

A buffered communication switch for switching multi-word data cells between input ports and selected output ports, comprising: a plurality of input ports for receiving incoming data cells; a plurality of output ports; a shared buffer memory for storing said incoming data cells received via said input ports while awaiting transmission via one or more of said output ports; a translator for examining said incoming data cells to designate one or more of said output ports for transmission of said incoming data cells; an address selector for selecting a vacant address in said shared buffer memory for storing an incoming data cell; means for storing said incoming data cell at said vacant address to provide a stored data cell and for storing the address thereof at said one or more output ports selected for transmission of said stored data cell; and means for retrieving coupled to said shared memory to receive said stored data cell at said address in said shared memory when time is available for transmission of said data cell via said selected one or more output ports; said means for storing and said means for retrieving being operable to transfer data cells to and from said shared buffer memory on a word-by-word basis.

Claim 20

A buffered communication switch according to claim 16 wherein said address selector includes means for maintaining a linked list of vacant addresses; means, coupled to said means for storage, for removing an address from said linked list when assigned for storage of a data cell; and means, coupled to said means for retrieving for adding an address to said linked list when the data cell stored at the address has been transmitted from all selected ports for said data cell.

Claim 21

A buffered communication switch: according to claim 16 wherein said address selector includes a memory map maintained to indicate currently assigned output ports for stored data cells; and a content addressable memory means using parallel flow through logic to determine a vacant address for storing said incoming data cell at said vacant address in said shared buffer memory.

Claim 22

A buffered communication switch according to claim 16 wherein said translator for examining incoming data cells also determines cell priority.

Claim 23

A buffered communication switch according to claim 19 for routing data cells according to virtual path and circuit designations in the data cell wherein said translator operates on a data compressed format according to the number of virtual paths and circuits being serviced.

Claim 24

A buffered communication switch according to claim 16 wherein said translator examines and translates the header of said incoming data cell and wherein other data cells are being transfered to and from said shared memory on a word-by-word basis while translations are being carried out.

Claim 25

A buffered communication switch according to claim 21 further including means for transmitting said data cell from one or more of said output ports when time is available; and further translator means for examining the header of each outgoing data cell and changing said header according to outgoing transmission link.

Claim 26

A buffered communication switch for the priority switching of multiword data cells between input ports and selected output ports, said data cells each having a data cell priority, comprising: one or more input ports for receiving incoming data cells; a plurality of output ports each including a plurality of priority address queues associated therewith; a shared buffer memory for storing said incoming data cells received via said one or more input ports while awaiting transmission via one or more of said output ports; a translator for examining said incoming data cells to determine the data cell priority, and to select one or more of said output ports for subsequent transmission of said incoming data cell; an address selector for selecting a vacant address in said shared buffer memory for storing an incoming data cell; means for storing said incoming data cell to provide a stored data cell at said vacant address and for storing the address thereof in a selected priority queue at each of said one or more output ports selected according to said cell priority; and means for retrieving coupled to said shared buffer memory to receive said stored data cell at a retrieval address in said shared memory when said retrieval address is at the head of the highest occupied priority queue at said selected port; said means for storing and said means for retrieving being operable to transfer data cells to and from said shared buffer memory on an interleaved word-by-word basis.

Claim 27

A buffered communication switch for the priority switching of multiword data cells between input ports and selected output ports, said data cells each having a data cell priority, comprising: one or more input ports for receiving incoming data cells; a plurality of output ports each including a plurality of priority address queues associated therewith; a shared buffer memory for storing said incoming data cells received via said one or more input ports while awaiting transmission via one or more of said output ports; a translator for examining said incoming data cells to determine the data cell priority, and to select one or more of said output ports for subsequent transmission of said incoming data cell; an address selector for selecting a vacant address in said shared buffer memory for storing an incoming data cell; means for storing said incoming data cell to provide a stored data cell at said vacant address and for storing the address thereof in a selected priority queue at each of said one or more output ports selected according to said cell priority; and means for retrieving coupled to said shared buffer memory to receive said stored data cell at a retrieval address in said shared memory when said retrieval address is at the head of the highest occupied priority queue at said selected port; said means for storing and said means for retrieving being operable to transfer data cells to and from said shared buffer memory on an interleaved word-by-word basis.

Claim 28

A buffered communication switch according to claim 23 wherein said address selector includes means for maintaining a linked list of vacant addresses; means, coupled to said means for storage, for removing an address from said linked list when assigned for storage of a data cell; and means, coupled to said means for retrieving, for adding an address to said linked list when the data cell stored at the address has been transmitted from all selected ports for said data cell.

Claim 29

A buffered communication switch according to claim 23 wherein said address selector includes a memory map maintained to indicate currently assigned exit ports for stored data cells; and a content addressable memory means using parallel flow through logic to determine a vacant address and for storing said incoming data cell at said vacant address in said shared buffer memory.

Claim 30

A buffered communication switch according to claim 23 for routing data cells according to virtual path and circuit designations in the data cell wherein said translator operates on a data compressed format according to the number of virtual paths and circuits being serviced.

Claim 31

A buffered communication switch according to claim 23 wherein said translator examines and translates the header of an incoming data cell while other data cells are being transferred to and from said shared memory on an interleaved word-by-word basis.

Claim 32

A buffered communication switch according to claim 23 further including means for transmitting said data cell from one or more of said output ports when time is available; and further translator means for examining the header of each outgoing data cell and changing said header according to outgoing transmission link.

Claim 35

The method according to claim 29 wherein said selection of a vacant address in the shared buffer memory includes maintaining a linked list of vacant addresses; removing an address from said linked list when assigned for storage of a data cell; and adding an address to said linked list when the data cell stored at the address has been transmitted from all selected ports for said data cell.

Claim 36

The method according to claim 29 wherein said selection of a vacant address in the shared buffer memory includes maintaining a memory map to indicate currently assigned exit ports for stored data cells; and using parallel flow through logic in a content addressable memory to determine a vacant address.

Claim 37

The method according to claim 29 wherein the header of said incoming data cell is examined and translated to determine the output port or ports and the cell priority.

Claim 38

The method according to claim 32 for routing data cells according to virtual path and circuit designations in the data cell wherein said translation is on a data compressed format according to the number of virtual paths and circuits being serviced.

Claim 39

The method according to claim 32 wherein the header of said incoming data cell is translated while other data cells are being transfered to and from said shared memory on a word-by-word basis.

Claim 40

The method according to claim 34 further including transmitting said data cell from one or more of said output ports when time is available, and translating the header of each outgoing data cell to change said header according to the outgoing transmission link.

Claim 41

The method according to claim 29 wherein said storing of said incoming data cell and said retrieving of said data cell is on a word-by-word interleaved basis.

Claim 44

The method according to claim 37 wherein said selection of a vacant address in the shared buffer memory includes maintaining a linked list of vacant addresses; removing an address from said linked list when assigned for storage of a data cell; and adding an address to said linked list when the data cell stored at the address has been transmitted from all selected ports for said data cell.

Claim 45

The method according to claim 37 wherein said selection of a vacant address in the shared buffer memory includes maintaining a memory map to indicate currently assigned exit ports for stored data cells; and using parallel flow through logic in a content addressable memory to determine a vacant address.

Claim 46

The method according to claim 37 wherein the header of said incoming data cell is examined and translated while other data cells are being transfered to and from said shared memory on a word-by-word basis.

Claim 47

The method according to claim 40 further including transmitting said data cell from one or more of said output ports when time is available, and translating the header of each outgoing data cell to change said header according to the outgoing transmission link.

Claim 48

The method according to claim 37 wherein said storing of said incoming data cell and said retrieving of said data cell is on a word-by-word interleaved basis.

Claim 51

The method according to claim 43 wherein said selection of a vacant address in the shared buffer memory includes maintaining a linked list of vacant addresses; removing an address from said linked list when assigned for storage of a data cell; and adding an address to said linked list when the data cell stored at the address has been transmitted from all selected ports for said data cell.

Claim 52

The method according to claim 43 wherein said selection of a vacant address in the shared buffer memory includes maintaining a memory map to indicate currently assigned exit ports for stored data cells; and using parallel flow through logic in a content addressable memory to determine a vacant address.

Claim 53

The method according to claim 43 wherein the header of said incoming data cell is examined and translated to determine the output port or ports and the cell priority.

Claim 54

The method according to claim 46 for routing data cells according to virtual path and circuit designations in the data cell wherein said translation is on a data compressed format according to the number of virtual paths and circuits being serviced.

Claim 55

The method according to claim 43 wherein the header of said incoming data cell is examined and translated while other data cells are being transfered to and from said shared memory on a word-by-word basis.

Claim 56

The method according to claim 48 further including transmitting said data cell from one or more of said output ports when time is available, and translating the header of each outgoing data cell to change said header according to the outgoing transmission link.

Claim 59

The method according to claim 50 wherein said selection of a vacant address in the shared buffer memory includes maintaining a linked list of vacant addresses; removing an address from said linked list when assigned for storage of a data cell; and adding an address to said linked list when the data cell stored at the address has been transmitted from all selected ports for said data cell.

Claim 60

The method according to claim 50 wherein said selection of a vacant address in the shared buffer memory includes maintaining a memory map to indicate currently assigned exit ports for stored data cells; and using parallel flow through logic in a content addressable memory to determine a vacant address.

Claim 61

The method according to claim 50 for routing data cells according to virtual path and circuit designations in the data cell wherein said examination of the received data cell includes a translation on a data compressed format according to the number of virtual paths and circuits being serviced.

Claim 62

The method according to claim 50 wherein the header of said incoming data cell is translated while other data cells are being transfered to and from said shared memory on a word-by-word basis.

Claim 63

The method according to claim 54 further including transmitting said data cell from one or more of said output ports when time is available, and translating the header of each outgoing data cell to change said header according to the outgoing transmission link.