US4823340A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for non-blocking switching of PCM channels in the space and time domain
Assignee: Bosch Telecom GmbH
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Filing: 1987-12-04
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Granted: 1989-04-18
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Expires: 2007-12-04
Abstract
Abstract A circuit arrangement for switching PCM channels conducting baseband data signals, with serial data to be switched arriving at n input ports and being converted in blocks to parallel form, intermediately stored in a memory and converted to serial form again after read-out to be fed to n output ports each assigned to one or a plurality of destination addresses. The parallel data blocks are intermediately stored the first time in n input registers assigned to the n input ports. Thereafter, a second intermediate storage takes place in a RAM memory in such a manner that the data blocks are written in successively according to the sequence in which they arrived at a memory address which is counted up sequentially, or the data are subsequently intermediately stored in a RAM memory at a memory address which corresponds to the respective destination address. The data blocks are read out according to the number of the output port contained in the destination address or assigned to the destination address or according to their time position and are again intermediately stored in n output registers which are assigned to the respective n output ports.
Inventors
- 👤 Wolfgang Grassman
- 👤 Walter Berner
- 👤 Gunter Muller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 04:52
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/08
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
336 words
In a circuit arrangement for switching PCM channels conducting baseband signals, the circuit arrangement including n input ports for receiving serial data to be switched, with n being at least 2, first conversion means connected to the input ports for converting serial data received by the input ports into blocks of data in parallel form, memory means for intermediately storing, and subsequently reading, out each block in parallel form, second conversion means connected for converting each block read out from the memory means to serial form, and n output ports each connected to receive the data of respective blocks converted to serial form from the second conversion means, in which the data in each data block formed by the first conversion means is intended to be conducted to a respective output port, the improvement comprising: n input registers each connected to said first conversion means for intermediately storing the parallel data blocks derived from the serial data received at a respective input port; n output registers each connected to said second conversion means, each associated with a respective output port, and each connected for intermediately storing those parallel data blocks read out of said memory means which are intended for the associated output port; and least one RAM memory forming part of said memory means and having a plurality of memory locations, each memory location having an address associated with one output port, said memory being operable for writing in data blocks from said input registers, in succession in the order in which the data contained in those data blocks arrives at said input ports, and storing each data block in a memory location associated with the output port to which the data in that block is to be conducted, and said memory further being operable for reading out the data blocks stored therein sequentially and for conducting each data block to that one of said output registers which is associated with the output port to which the data in that block is to be conducted.
Claim 2
Dependent Claim
336 words
In a circuit arrangement for switching PCM channels conducting baseband signals, the circuit arrangement including n input ports for receiving serial data to be switched, with n being at least 2, first conversion means connected to the input ports for converting serial data received by the input ports into blocks of data in parallel form, memory means for intermediately storing, and subsequently reading, out each block in parallel form, second conversion means connected for converting each block read out from the memory means to serial form, and n output ports each connected to receive the data of respective blocks converted to serial form from the second conversion means, in which the data in each data block formed by the first conversion means is intended to be conducted to a respective output port, the improvement comprising: n input registers each connected to said first conversion means for intermediately storing the parallel data blocks derived from the serial data received at a respective input port; n output registers each connected to said second conversion means, each associated with a respective output port, and each connected for intermediately storing those parallel data blocks read out of said memory means which are intended for the associated output port; and least one RAM memory forming part of said memory means and having a plurality of memory locations, each memory location having an address associated with one output port, said memory being operable for writing in data blocks from said input registers, in succession in the order in which the data contained in those data blocks arrives at said input ports, and storing each data block in a memory location associated with the output port to which the data in that block is to be conducted, and said memory further being operable for reading out the data blocks stored therein sequentially and for conducting each data block to that one of said output registers which is associated with the output port to which the data in that block is to be conducted.
Claim 3
Dependent Claim
43 words
Circuit arrangement as defined in claim 1 wherein there are two said RAM memories connected and operated such each said memory is alternatingly read out and written into, with one said memory being read out while the other said memory is written into.
Claim 4
Dependent Claim
24 words
Circuit arrangement as defined in claim 1 further comprises a counter connected for controlling the sequential writing of the data blocks to said memory.
Claim 5
Dependent Claim
54 words
Circuit arrangement as defined in claim 1 wherein the serial data arriving at said input ports includes destination information identifying the output port to which that data is to be conducted, and further comprising separating means connected for separating the destination information from the data before each data block is written into said memory.
Claim 6
Dependent Claim
34 words
Circuit arrangement as defined in claim 1 wherein information identifying the output port to which the data in each data block is to be conducted is supplied to said arrangement from an external source.
Claim 7
Dependent Claim
49 words
Circuit arrangement as defined in claim 1 further comprising means for subjecting th serial data arriving at said input ports to coding so as to generate an error correctable or error correcting code and means for subjecting the serial data arriving at said output ports to a corresponding decoding.
Claim 8
Dependent Claim
44 words
Circuit arrangement as defined in claim 1 wherein the serial data supplied to said input ports are present as 64-bit TDM signals within a frame of about 2200 voice channels and are supplied to each input port with a frame duration of 1 ms.
Claim 9
Dependent Claim
24 words
Circuit arrangement as defined in claim 1 composed of a plurality of modules each having four said input ports and four said output ports.
Claim 10
Dependent Claim
304 words
In a circuit arrangement for switching PCM channels conducting baseband signals, the circuit arrangement including n input ports for receiving serial data to be switched, ith n being at least 2, first conversion means connected to the input ports for converting serial data received by the input ports into blocks of data in parallel form, memory means for intermediately storing, and subsequently reading, out each block in parallel form, second conversion means connected for converting each block read out from the memory means to serial form, and n output ports each connected to receive the data of respective blocks converted to serial form from the second conversion means, in which the data in each data block formed by the first conversion means is intended to be conducted to a respective output port, the improvement comprising: n input registers each connected to said first conversion means for intermediately storing the parallel data blocks derived from the serial data received at a respective input port; n output registers each connected to said second conversion means, each associated with a respective output port, and each connected for intermediately storing those parallel data blocks read out of said memory means which are intended for the associated output port; and least one RAM memory forming part of said memory means and having a plurality of memory locations, said memory being operable for writing in data blocks in succession from said input registers, in the order in which the data contained in those data blocks arrives at said input ports and in successive memory locations, said memory further being operable for reading out the data blocks stored therein sequentially and for conducting each data block to that one of said output registers which is associated with the output port to which the data in that block is to be conducted.
Claim 11
Dependent Claim
304 words
In a circuit arrangement for switching PCM channels conducting baseband signals, the circuit arrangement including n input ports for receiving serial data to be switched, ith n being at least 2, first conversion means connected to the input ports for converting serial data received by the input ports into blocks of data in parallel form, memory means for intermediately storing, and subsequently reading, out each block in parallel form, second conversion means connected for converting each block read out from the memory means to serial form, and n output ports each connected to receive the data of respective blocks converted to serial form from the second conversion means, in which the data in each data block formed by the first conversion means is intended to be conducted to a respective output port, the improvement comprising: n input registers each connected to said first conversion means for intermediately storing the parallel data blocks derived from the serial data received at a respective input port; n output registers each connected to said second conversion means, each associated with a respective output port, and each connected for intermediately storing those parallel data blocks read out of said memory means which are intended for the associated output port; and least one RAM memory forming part of said memory means and having a plurality of memory locations, said memory being operable for writing in data blocks in succession from said input registers, in the order in which the data contained in those data blocks arrives at said input ports and in successive memory locations, said memory further being operable for reading out the data blocks stored therein sequentially and for conducting each data block to that one of said output registers which is associated with the output port to which the data in that block is to be conducted.
Claim 12
Dependent Claim
43 words
Circuit arrangement as defined in claim 9 wherein there are two said RAM memories connected and operated such each said memory is alternatingly read out and written into, with one said memory being read out while the other said memory is written into.
Claim 13
Dependent Claim
25 words
Circuit arrangement as defined in claim 9 further comprising a counter connected for controlling the sequential writing in of the data blocks to said memory.
Claim 14
Dependent Claim
55 words
Circuit arrangement as defined in claim 9 wherein the serial data arriving at said input ports includes destination information identifying the output port to which that data is to be conducted, and further comprising separating means connected for separating the destination information from the data before each data block is written in to said memory.
Claim 15
Dependent Claim
34 words
Circuit arrangement as defined in claim 9 wherein information identifying the output port to which the data in each data block is to be conducted is supplied to said arrangement from an external source.
Claim 16
Dependent Claim
49 words
Circuit arrangement as defined in claim 9 further comprising means for subjecting the serial data arriving at said input ports to coding so as to generate an error correctable or error correcting code and means for subjecting the serial data arriving at said output ports to a corresponding decoding.
Claim 17
Dependent Claim
44 words
Circuit arrangement as defined in claim 9 wherein the serial data supplied to said input ports are present as 64-bit TDM signals within a frame of about 2200 voice channels and are supplied to each input port with a frame duration of 1 ms.
Claim 18
Dependent Claim
24 words
Circuit arrangement as defined in claim 9, composed of a plurality of modules each having four said input ports and four said output ports.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-17 | 1992-10-17 | 1993-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-17 | 1996-10-17 | 1997-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-17 | 2000-10-17 | 2001-04-18 | $7700.00 | Window Closed / Lapsed |