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Patent US5973632A successfully refreshed from Google Patents.
US5973632A
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Sub-range flash analog-to-digital converter
Assignee: Powerchip Technology Corp
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Filing: 1998-03-03
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Granted: 1999-10-26
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Expires: 2018-03-03
Abstract
Abstract A sub-range flash ADC having correction circuits for dealing with conversion errors induced by the coarse comparison in the thermal code format. Fine thermal codes accompanied by extension codes may be used to decide whether a conversion error has happened and what kind of conversion error it is. After determining whether a conversion error has occurred, the coarse thermal codes are shifted right or left by one bit, similar to the addition or subtraction mathematical operation, to obtain corrected coarse thermal codes. In addition, the fine thermal codes (including the extension thermal codes) are shifted left or right by a bit length equal to the fine thermal codes, similar to the subtraction and addition operation, to obtain corrected fine thermal codes. These corrected coarse and fine thermal codes can be directly used for encoding without any further correction process.
Inventors
- 👤 Jy-Der David Tai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:35
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/0617; H03M1/0675; H03M1/069; H03M1/12; H03M1/14; H03M1/145
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
327 words
A sub-range flash analog-to-digital converter for converting an input analog signal to an output digital signal having a fixed bit length, said sub-range flash analog-to-digital converter comprising: a reference voltage generator for generating a plurality of coarse reference voltages for coarse comparison, a plurality of fine reference voltages for fine comparison and a plurality of extension reference voltages for correcting the mismatch between the coarse comparison and the fine comparison; a coarse thermal code generator for receiving the input analog signal, comparing the input analog signal with the coarse reference voltages, and generating a first set of thermal codes associated with most significant bits of the output digital signal; a fine thermal code generator for receiving the input analog signal, comparing an intermediate analog signal proportional to the input analog signal with the fine reference voltages and the extension reference voltages, and generating a second set of thermal codes associated with least significant bits of the output digital signal and a third set of thermal codes associated with the comparison of the intermediate analog signal and the extension reference voltages; a first correction circuit for modifying the first set of the thermal codes in response to the second and the third sets of the thermal codes and generating a set of modified coarse thermal codes, when the second and third sets of the thermal codes indicate that the intermediate analog signal is out of a voltage range defined by the fine reference voltages; a second correction circuit for modifying the second set of the thermal codes in response to the second and third sets of the thermal codes and generating a set of modified fine thermal codes, when the second and third sets of the thermal codes indicate that the intermediate analog signal is out of a voltage range defined by the fine reference voltages; and an encoder for generating the output digital signal according to the modified coarse thermal codes and the modified fine thermal codes.
Claim 2
Dependent Claim
327 words
A sub-range flash analog-to-digital converter for converting an input analog signal to an output digital signal having a fixed bit length, said sub-range flash analog-to-digital converter comprising: a reference voltage generator for generating a plurality of coarse reference voltages for coarse comparison, a plurality of fine reference voltages for fine comparison and a plurality of extension reference voltages for correcting the mismatch between the coarse comparison and the fine comparison; a coarse thermal code generator for receiving the input analog signal, comparing the input analog signal with the coarse reference voltages, and generating a first set of thermal codes associated with most significant bits of the output digital signal; a fine thermal code generator for receiving the input analog signal, comparing an intermediate analog signal proportional to the input analog signal with the fine reference voltages and the extension reference voltages, and generating a second set of thermal codes associated with least significant bits of the output digital signal and a third set of thermal codes associated with the comparison of the intermediate analog signal and the extension reference voltages; a first correction circuit for modifying the first set of the thermal codes in response to the second and the third sets of the thermal codes and generating a set of modified coarse thermal codes, when the second and third sets of the thermal codes indicate that the intermediate analog signal is out of a voltage range defined by the fine reference voltages; a second correction circuit for modifying the second set of the thermal codes in response to the second and third sets of the thermal codes and generating a set of modified fine thermal codes, when the second and third sets of the thermal codes indicate that the intermediate analog signal is out of a voltage range defined by the fine reference voltages; and an encoder for generating the output digital signal according to the modified coarse thermal codes and the modified fine thermal codes.
Claim 3
Dependent Claim
70 words
The sub-range flash analog-to-digital converter as recited in claim 1, further comprising: a control circuit for generating a first control signal and a second control signal in response to the second and third of the thermal codes, the first control signal being transmitted to the first correction circuit to perform the modifying operation and the second control signal being transmitted to the second correction circuit to perform the modifying operation.
Claim 4
Dependent Claim
34 words
The sub-range flash analog-to-digital converter as recited in claim 2, wherein the first and second correction circuits are implemented by shift registers controlled by the first control signal and the second control signal, respectively.
Claim 5
Dependent Claim
33 words
The sub-range flash analog-to-digital converter as recited in claim 2, wherein the first and second correction circuits are implemented by multiplexers controlled by the first control signal and the second control signal, respectively.
Claim 6
Dependent Claim
85 words
The sub-range flash analog-to-digital converter as recited in claim 1, wherein the first correction circuit shifts the first set of the thermal codes left by one bit to obtain the modified coarse thermal codes when the intermediate analog signal exceeds the voltage range defined by the fine reference voltages, and shifts the first set of the thermal codes right by one bit to obtain the modified coarse thermal codes when the intermediate analog signal is below the voltage range defined by the fine reference voltages.
Claim 7
Dependent Claim
100 words
The sub-range flash analog-to-digital converter as recited in claim 1, wherein the second correction circuit shifts the second and third sets of the thermal codes right by a bit length equal to the second set of the thermal codes to obtain the modified fine thermal codes when the intermediate analog signal exceeds the voltage range defined by the fine reference voltages, and shifts the second and third sets of the thermal codes left by the bit length to obtain the modified fine thermal codes when the intermediate analog signal is below the voltage range defined by the fine reference voltages.
Claim 8
Dependent Claim
38 words
The sub-range flash analog-to-digital converter as recited in claim 1, wherein the extension reference voltages includes a plurality of upper voltages higher than the fine reference voltages and a plurality of lower voltages below the fine reference voltages.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-25 | 2003-04-26 | 2003-10-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-25 | 2007-04-26 | 2007-10-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-25 | 2011-04-26 | 2011-10-26 | $7700.00 | Window Closed / Lapsed |