Tri-step analog-to-digital converter

Claim 2

A tri-step analog-to-digital converter for the conversion of an analog input voltage signal to an output digital code, comprising: a) a sample and hold means to sample at periodic intervals the analog input voltage signal and hold the sampled analog input signal during the conversion; b) a reference voltage generator coupled between a first reference voltage source and second reference voltage source to create a plurality of reference voltages from said first and second voltage sources; c) a reference voltage selection switch network connected to the plurality of reference voltages; d) a coarse resolution analog-to-digital converter coupled to the sampled analog input signal to convert said sampled analog input signal to a coarse digital code; e) a sub-coarse resolution analog-to-digital converter coupled to the sampled analog input signal to convert said sampled analog input signal to a sub-coarse digital code; f) a fine resolution analog-to-digital converter coupled to the sampled analog input signal to convert said sampled analog input signal to a fine digital code; g) a reference voltage selection logic means coupled to the reference voltage selection switch network to select a coupling of the plurality of reference voltages to the sub-coarse and fine analog-to-digital converter's; and h) an output encoding means to translate the coarse digital code, the sub-coarse digital code, and the fine digital code to an output digital code.

Claim 3

The converter of claim 1 wherein the reference voltage generator comprises a first resistor connected to the first reference voltage source, a last resistor connected to the second reference voltage source, and plurality of serially connected resistors coupled between the first and last resistors.

Claim 4

The converter of claim 2 wherein the voltage developed at each connection of the plurality of serial connected resistors is one of the plurality reference voltages, the voltage difference of the voltages developed at two adjacent connections of the plurality of serial connected resistors equals to: (V.sub.REF1 -V.sub.REF2)/2.sup.n Where V REF1 is magnitude of the first reference voltage source, V REF2 is the magnitude of the second reference voltage source, and n is the number of bits in the output digital code.

Claim 5

The converter of claim I wherein the coarse resolution analog-to-digital converter comprises: a) a first plurality of voltage comparators, wherein each comparator comprises a voltage input terminal coupled to the analog input voltage signal, a voltage reference terminal coupled to one of the plurality of reference voltages, a compare output terminal where a comparator output signal is placed, and a voltage comparing means that will generate the comparator output signal that has a first state if the analog input voltage signal present at the input terminal is larger than the reference voltage present at the reference voltage terminal, and a second state if the analog input voltage present at the input terminal is less than the reference voltage present at the reference voltage terminal; and b) a coarse digital encoder for translating the comparator output signals from the first plurality of voltage comparators to said coarse digital code that represents a coarse approximation of the magnitude of the analog input signal.

Claim 6

The converter of claim 4 wherein the coarse digital code forms the most significant bits of the output digital word.

Claim 7

The converter of claim 1 wherein the reference voltage selection switch comprises: a) a plurality of sub-coarse resolution selection switches to selectively couple a first subset of the plurality of voltage references to the sub-coarse resolution analog-to-digital converter; and b) a plurality of fine resolution selection switches to selectively couple a second subset of the plurality of voltage references to the fine resolution analog-to-digital converter.

Claim 8

The converter of claim 6 wherein the reference voltage selection logic means comprises: a) a coarse digital code input terminal connected to the coarse analog-to-digital converter; b) a sub-coarse digital code input terminal connected to the subcoarse analog-to digital converter; c) a sub-coarse switch location resolution means to determine the activation of the plurality of sub-coarse resolution selection switches based on the coarse digital code; and d) a fine switch location resolution means to determine the activation of fine resolution selection switches based on the coarse digital code and the sub-coarse digital code.

Claim 9

The converter of claim 1 wherein the sub-coarse resolution analog-to-digital converter comprises: a) a second plurality of voltage comparators, wherein each comparator comprises a voltage input terminal coupled to the analog input voltage signal, a voltage reference terminal coupled to one of the sub-coarse reference voltages, a compare output terminal where a comparator output signal is placed, and a voltage comparing means that will generate the comparator output signal that has a first state if the analog input voltage signal present at the input terminal is larger than the sub-coarse reference voltage present at the reference voltage terminal; and a second state if the analog input voltage present at the input terminal is less than the sub-coarse reference voltage present at the reference voltage terminal, and b) a sub-coarse resolution digital encoder for translating the comparator output signals from the second plurality of voltage comparators to said sub-coarse digital code that represents an intermediate refinement of the coarse approximation of the magnitude of the analog input signal.

Claim 10

The converter of claim 8 wherein the sub-coarse digital code form the intermediate significant bits of the digital output code.

Claim 11

The converter of claim 1 wherein the fine resolution analog-to-digital converter comprises: a) a third plurality of voltage comparators, wherein each comparator comprises a voltage input terminal coupled to the analog input voltage signal, a voltage reference terminal coupled to the fine voltage references, a compare output terminal where a comparator output signal is placed, and a voltage comparing means that will generate the comparator output signal that has a first state if the analog input voltage signal present at the input terminal is larger than the fine reference voltage present at the reference voltage terminal, and a second state if the analog input voltage present at the input terminal is less than the fine reference voltage present at the reference voltage terminal; and b) a fine resolution digital encoder for translating the comparator output signals of the third plurality of comparators to said fine digital code that represents a fine determination of the coarse approximation of the analog input signal.

Claim 12

The converter of claim 10 wherein the fine digital code forms the least significant bits and a correction factor to the intermediate significant bits.

Claim 13

The converter of claim 1 wherein the output digital code is a binary number comprising a set of most significant bits, a set of intermediate significant bits, and a set of least significant bits.

Claim 14

A three stage analog-to-digital converter for the conversion of an analog input signal to a digital output code, comprising a) a sample and hold means to sample at periodic alternate first sampling and second sampling intervals of time the analog input voltage signal and hold the sampled analog input signal during the conversion; b) a reference voltage generator coupled between a first reference voltage source and second reference voltage source to create a plurality of reference voltages from said first and second voltage sources; c) a reference voltage selection switch network connected to the plurality of reference voltages; d) a coarse voltage comparing means coupled to the sampled analog input signal to convert said analog input signal to a set of coarse thermometer codes; e) a coarse encoder to convert the set of coarse thermometer codes to a set of coarse digital codes representing a coarse approximation of the magnitude of the sampled analog input signal; f) a first sub-coarse voltage comparing means coupled to the analog input signal to convert said analog input signal to a set of first sub-coarse thermometer codes; g) a second sub-coarse voltage comparing means coupled to the analog input signal to convert said analog input signal to a set of second sub-coarse thermometer codes; h) a first sub-coarse encoder to convert the set of first sub-coarse thermometer codes to a first set of sub-coarse digital codes; i) a second sub-coarse encoder to convert the set of first sub-coarse thermometer codes to a second set of sub-coarse digital codes; j) a first fine voltage comparing means coupled to the analog input signal to convert said analog input signal to a set of first fine thermometer codes; k) a second fine voltage comparing means coupled to the analog input signal to convert said analog input signal to a set of second fine thermometer codes; l) a first fine encoder to convert the set of first fine thermometer codes to a first set of fine digital codes; m) a second fine encoder to convert the set of second fine thermometer codes to a second set of fine digital codes; n) a reference voltage selection logic means coupled to the reference voltage selection switch network to select a coupling of the plurality of reference voltages to the sub-coarse and fine analog-to-digital converters; and o) an output encoding means to translate the coarse digital code, the sub-coarse digital code, and the fine digital code to an output digital code comprising n bits.

Claim 15

A three stage analog-to-digital converter for the conversion of an analog input signal to a digital output code, comprising a) a sample and hold means to sample at periodic alternate first sampling and second sampling intervals of time the analog input voltage signal and hold the sampled analog input signal during the conversion; b) a reference voltage generator coupled between a first reference voltage source and second reference voltage source to create a plurality of reference voltages from said first and second voltage sources; c) a reference voltage selection switch network connected to the plurality of reference voltages; d) a coarse voltage comparing means coupled to the sampled analog input signal to convert said analog input signal to a set of coarse thermometer codes; e) a coarse encoder to convert the set of coarse thermometer codes to a set of coarse digital codes representing a coarse approximation of the magnitude of the sampled analog input signal; f) a first sub-coarse voltage comparing means coupled to the analog input signal to convert said analog input signal to a set of first sub-coarse thermometer codes; g) a second sub-coarse voltage comparing means coupled to the analog input signal to convert said analog input signal to a set of second sub-coarse thermometer codes; h) a first sub-coarse encoder to convert the set of first sub-coarse thermometer codes to a first set of sub-coarse digital codes; i) a second sub-coarse encoder to convert the set of first sub-coarse thermometer codes to a second set of sub-coarse digital codes; j) a first fine voltage comparing means coupled to the analog input signal to convert said analog input signal to a set of first fine thermometer codes; k) a second fine voltage comparing means coupled to the analog input signal to convert said analog input signal to a set of second fine thermometer codes; l) a first fine encoder to convert the set of first fine thermometer codes to a first set of fine digital codes; m) a second fine encoder to convert the set of second fine thermometer codes to a second set of fine digital codes; n) a reference voltage selection logic means coupled to the reference voltage selection switch network to select a coupling of the plurality of reference voltages to the sub-coarse and fine analog-to-digital converters; and o) an output encoding means to translate the coarse digital code, the sub-coarse digital code, and the fine digital code to an output digital code comprising n bits.

Claim 16

The converter of claim 13 wherein the reference voltage generator comprises a first resistor connected to the first reference voltage source, a last resistor connected to the second reference voltage source, and plurality of serially connected resistors coupled between the first and last resistors.

Claim 17

The converter of claim 14 wherein the voltage developed at each connection of the plurality of serial connected resistors is one of the plurality reference voltages, and the voltage difference of the voltages developed at two adjacent connections of the plurality of serial connected resistors equals to (V.sub.REF1 -V.sub.REF2)/2.sup.n Where V REF1 is magnitude of the first reference voltage source, V REF2 is the magnitude of the second reference voltage source, and n is the n bits in the output digital code.

Claim 18

The converter of claim 13 wherein the reference voltage selection switch comprises: a) a plurality of sub-coarse resolution selection switches to selectively couple a first subset of the plurality of voltage references to the sub-coarse resolution analog-to-digital converter; and b) a plurality of fine resolution selection switches to selectively couple a second subset of the plurality of voltage references to the fine resolution analog-to-digital converter.

Claim 19

The converter of claim 16 wherein the reference voltage selection logic means comprises: a) a coarse digital code input terminal connected to the coarse comparator mean; b) a first sub-coarse digital code input terminal connected to the first sub-coarse encoder; c) a second sub-coarse digital code input terminal connected to the second sub-coarse encoder; d) a sub-coarse switch location resolution means to determine the activation of the plurality of sub-coarse resolution selection switches based on the coarse digital code; and e) a fine switch location resolution means to determine the activation of fine resolution selection switches based on the coarse digital code and the sub-coarse digital code.

Claim 20

The converter of claim 13 wherein the output digital code is a binary number comprising a set of most significant bits, a set of intermediate significant bits, and a set of least significant bits.

Claim 21

The converter of claim 13 wherein the coarse digital code forms the most significant bits of the output digital word.

Claim 22

The converter of claim 13 wherein the first sub-coarse comparator means comprises a) a voltage input terminal coupled to the analog input voltage signal; b) a voltage reference terminal coupled to one of the plurality of reference voltages; c) a compare output terminal where a comparator output signal is placed; and d) a voltage comparing means that will generate the comparator output signal that has a first state if the analog input voltage signal present at the input terminal is larger than the reference voltage present at the reference voltage terminal, and a second state if the analog input voltage present at the input terminal is less than the reference voltage present at the reference voltage terminal.

Claim 23

The converter of claim 13 wherein the second sub-coarse comparator means comprises a) a voltage input terminal coupled to the analog input voltage signal; b) a voltage reference terminal coupled to one of the plurality of reference voltages; c) a compare output terminal where a comparator output signal is placed; and d) a voltage comparing means that will generate the comparator output signal that has a first state if the analog input voltage signal present at the input terminal is larger than the reference voltage present at the reference voltage terminal, and a second state if the analog input voltage present at the input terminal is less than the reference voltage present at the reference voltage terminal.

Claim 24

The converter of claim 13 wherein the first fine comparator means comprises a) a voltage input terminal coupled to the analog input voltage signal; b) a voltage reference terminal coupled to the fine voltage references; c) a compare output terminal where a comparator output signal is placed; and d) a voltage comparing means that will generate the comparator output signal that has a first state if the analog input voltage signal present at the input terminal is larger than the fine reference voltage present at the reference voltage terminal, and a second state if the analog input voltage present at the input terminal is less than the fine reference voltage present at the reference voltage terminal.

Claim 25

The converter of claim 13 wherein the second fine comparator means comprises: a) a voltage input terminal coupled to the analog input voltage signal; b) a voltage reference terminal coupled to the fine voltage references; c) a compare output terminal where a comparator output signal is placed; and d) a voltage comparing means that will generate the comparator output signal that has a first state if the analog input voltage signal present at the input terminal is larger than the fine reference voltage present at the reference voltage terminal, and a second state if the analog input voltage present at the input terminal is less than the fine reference voltage present at the reference voltage terminal.

Claim 26

The converter of claim 13 wherein at said first sampling interval, the conversion of said analog input signal to the output digital code is performed by the coarse comparing means, coarse encoding means, the first sub-coarse comparing means, the first sub-coarse encoder, the first fine comparing means, the first fine encoder, and the output encoding means.

Claim 27

The converter of claim 13 wherein at said second sampling intervals, the conversion of said analog input to the output digital code is performed by the coarse comparing means, coarse encoding means, the second subcoarse comparing means, the second sub-coarse encoder, the second fine comparing means, the second fine encoder, and the output encoding means.

Claim 30

The method of claim 26 wherein the respectively comparing of the sampled analog signals at said first and second sampling intervals to the set of fine reference voltages further forms a first and second error correction codes for being utilized in the encoding of the first and the second output digital codes.