Two-step parallel A/D converter

Claim 2

A two-step parallel A/D converter for performing A/D conversion of an input analog signal by upper bit conversion and lower bit conversion, comprising: means for expanding a first voltage range for the upper bit conversion to set a second voltage range for the lower bit conversion by amplifying upper and lower limit voltages of the first voltage range on the basis of a median voltage thereof, irrespective of a voltage of the input analog signal.

Claim 3

A two-step parallel A/D converter for performing A/D conversion of an input analog signal by upper bit conversion and lower bit conversion, comprising: means for obtaining a high level reference voltage for lower bit conversion by amplifying an upper limit voltage of a voltage range for lower bit conversion on the basis of a median voltage of the voltage range; means for obtaining lower level reference voltage for lower bit conversion by amplifying a lower limit voltage of the voltage range on the basis of the median voltage of the voltage range; and means for obtaining lower bit data depending on a position between the high level reference voltage and the low level reference voltage occupied by a voltage obtained by amplifying a voltage of the analog signal on the basis of the median voltage of the voltage range.

Claim 4

A two-step parallel A/D converter for performing A/D conversion of an input analog signal by upper bit conversion and lower bit conversion, comprising: means for obtaining a high level reference voltage for lower bit conversion by amplifying an upper limit voltage of a voltage range for lower bit conversion on the basis of a median voltage of the voltage range; means for obtaining lower level reference voltage for lower bit conversion by amplifying a lower limit voltage of the voltage range on the basis of the median voltage of the voltage range; and means for obtaining lower bit data depending on a position between the high level reference voltage and the low level reference voltage occupied by a voltage obtained by amplifying a voltage of the analog signal on the basis of the median voltage of the voltage range.

Claim 5

A two-step parallel A/D converter for performing A/D conversion of an input analog signal by upper bit conversion and lower bit conversion, comprising: an upper bit converting section for dividing a portion between a predetermined high level reference voltage and a predetermined low level reference voltage into a plurality of reference voltage ranges, obtaining a reference voltage range to which a voltage of the analog signal belongs from the reference voltage ranges obtained by the division, generating and outputting bit data indicative of the obtained reference voltage range as upper bit data, and outputting an upper limit voltage, a lower limit voltage and a median voltage of a voltage range for lower bit conversion determined on the basis of the obtained reference voltage range; a first differential amplifier for inputting the analog signal and the median voltage of the voltage range for lower bit conversion which is output from the upper bit converting section and amplifying the voltage of the analog signal on the basis of the median voltage; a second differential amplifier having the same gain as that of the first differential amplifier, serving to input the upper limit voltage and the median voltage of the voltage range for lower bit conversion which is output from the upper bit converting section and to amplify the upper limit voltage on the basis of the median voltage; a third differential amplifier having the same gain as those of the first and second differential amplifiers, serving to input the lower limit voltage and the median voltage of the voltage range for lower bit conversion which is output from the upper bit converting section and to amplify the lower limit voltage on the basis of the median voltage; and a lower bit converting section for setting an output voltage of the second differential amplifier to a high level reference voltage for lower bit conversion, setting an output voltage of the third differential amplifier to a low level reference voltage for lower bit conversion, dividing a portion between the high level reference voltage and the lower level reference voltage into a plurality of reference voltage ranges, obtaining a reference voltage range to which the output voltage of the first differential amplifier belongs from the reference voltage ranges obtained by the division, and generating and outputting, as lower bit data, bit data indicative of the obtained reference voltage range.

Claim 6

A two-step parallel A/D converter for performing A/D conversion of an input analog signal by upper bit conversion and lower bit conversion, comprising: an upper bit converting section for dividing a portion between a predetermined high level reference voltage and a predetermined low level reference voltage into a plurality of reference voltage ranges, obtaining a reference voltage range to which a voltage of the analog signal belongs from the reference voltage ranges obtained by the division, generating and outputting bit data indicative of the obtained reference voltage range as upper bit data, and outputting an upper limit voltage, a lower limit voltage and a median voltage of a voltage range for lower bit conversion determined on the basis of the obtained reference voltage range; a first differential amplifier for inputting the analog signal and the median voltage of the voltage range for lower bit conversion which is output from the upper bit converting section and amplifying the voltage of the analog signal on the basis of the median voltage; a second differential amplifier having the same gain as that of the first differential amplifier, serving to input the upper limit voltage and the median voltage of the voltage range for lower bit conversion which is output from the upper bit converting section and to amplify the upper limit voltage on the basis of the median voltage; a third differential amplifier having the same gain as those of the first and second differential amplifiers, serving to input the lower limit voltage and the median voltage of the voltage range for lower bit conversion which is output from the upper bit converting section and to amplify the lower limit voltage on the basis of the median voltage; and a lower bit converting section for setting an output voltage of the second differential amplifier to a high level reference voltage for lower bit conversion, setting an output voltage of the third differential amplifier to a low level reference voltage for lower bit conversion, dividing a portion between the high level reference voltage and the lower level reference voltage into a plurality of reference voltage ranges, obtaining a reference voltage range to which the output voltage of the first differential amplifier belongs from the reference voltage ranges obtained by the division, and generating and outputting, as lower bit data, bit data indicative of the obtained reference voltage range.

Claim 7

The two-step parallel A/D converter of claim 3, further comprising a fourth differential amplifier having the same gain as those of the first to third differential amplifiers, and serving to amplify the median voltage of the voltage range for lower bit conversion which is output from the upper bit converting section, on the basis of the median voltage, an output voltage of the fourth differential amplifier being input, to the lower bit converting section, as a median reference voltage of a voltage range from the high level reference voltage to the low level reference voltage for lower bit conversion.

Claim 8

The two-step parallel A/D converter of claim 3, wherein the upper bit converting section serves to output an upper limit voltage, a lower limit voltage and a median voltage of a predetermined voltage range and a median voltage of a voltage range for lower bit conversion in place of the upper limit voltage, the lower limit voltage and the median voltage of the voltage range for lower bit conversion, the second differential amplifier serves to input the upper limit voltage and the median voltage of the predetermined voltage range which are output from the upper bit converting section, and to amplify the upper limit voltage on the basis of the median voltage, and the third differential amplifier serves to input the lower limit voltage and the median voltage of the predetermined voltage range which are output from the upper bit converting section, and to amplify the lower limit voltage on the basis of the median voltage.

Claim 9

The two-step parallel A/D converter of claim 3, wherein the upper bit converting section serves to compare each median voltage of the reference voltage ranges obtained by the division with the voltage of the analog signal to select two adjacent reference voltage ranges, in which the voltage of the analog signal is higher than the median voltage of one reference voltage range and lower than the median voltage for the other, and to set bit data indicative of one of the two adjacent reference voltage ranges to upper bit data and to obtain a voltage range for lower bit conversion by adding the two adjacent reference voltage ranges.

Claim 10

The two-step parallel A/D converter of claim 6, wherein the upper bit converting section serves to output, as the upper bit data, bit data indicative of a lower voltage range of the two adjacent reference voltage ranges, the two-step parallel A/D converter serving to perform correction by adding "1" to the upper bit data output from the upper bit converting section when MSB of the lower bit data output from the lower bit converting section is "1".

Claim 11

The two-step parallel A/D converter of claim 3, wherein the upper bit converting section includes an upper buffer for latching and outputting the generated upper bit data in response to a given pulse signal, and the lower bit converting section includes a lower buffer for latching and outputting the generated lower bit data in response to a given pulse signal, the two-step parallel A/D converter further comprising a lower-upper buffer for latching and outputting the upper bit data output from the upper buffer and the lower bit data output from the lower buffer in response to a given pulse signal.

Claim 12

A two-step parallel A/D converter for performing A/D conversion of an input analog signal by upper bit conversion and lower bit conversion, comprising: an upper bit converting section for dividing a portion between a predetermined high level reference voltage and a predetermined low level reference voltage into a plurality of reference voltage ranges, obtaining a reference voltage range to which a voltage of the analog signal belongs from the reference voltage ranges obtained by the division, and coding upper bits according to the obtained reference voltage ranges; a first differential amplifier for amplifying the voltage of the analog signal on the basis of a median voltage of the reference voltage range obtained by the upper bit converting section; a second differential amplifier having the same gain as that of the first differential amplifier and serving to amplify an upper limit voltage of the reference voltage range on the basis of a median voltage of the reference voltage range obtained by the upper bit converting section; a third differential amplifier having the same gain as those of the first and second differential amplifiers and serving to amplify a lower limit voltage of the reference voltage range on the basis of a median voltage of the reference voltage range obtained by the upper bit converting section; and a lower bit converting section for setting an output voltage of the second differential amplifier to a high level reference voltage for lower bit conversion, setting an output voltage of the third differential amplifier to a low level reference voltage for lower bit conversion, dividing a portion between the high level reference voltage and the low level reference voltage into a plurality of reference voltage ranges, obtaining a reference voltage range to which an output voltage of the first differential amplifier belongs from the reference voltage ranges obtained by the division, and coding lower bits in accordance with the obtained reference voltage ranges.

Claim 13

A two-step parallel A/D converter for performing A/D conversion of an input analog signal by upper bit conversion and lower bit conversion, comprising: an upper bit converting section for dividing a portion between a predetermined high level reference voltage and a predetermined low level reference voltage into a plurality of reference voltage ranges, obtaining a reference voltage range to which a voltage of the analog signal belongs from the reference voltage ranges obtained by the division, and coding upper bits according to the obtained reference voltage ranges; a first differential amplifier for amplifying the voltage of the analog signal on the basis of a median voltage of the reference voltage range obtained by the upper bit converting section; a second differential amplifier having the same gain as that of the first differential amplifier and serving to amplify an upper limit voltage of the reference voltage range on the basis of a median voltage of the reference voltage range obtained by the upper bit converting section; a third differential amplifier having the same gain as those of the first and second differential amplifiers and serving to amplify a lower limit voltage of the reference voltage range on the basis of a median voltage of the reference voltage range obtained by the upper bit converting section; and a lower bit converting section for setting an output voltage of the second differential amplifier to a high level reference voltage for lower bit conversion, setting an output voltage of the third differential amplifier to a low level reference voltage for lower bit conversion, dividing a portion between the high level reference voltage and the low level reference voltage into a plurality of reference voltage ranges, obtaining a reference voltage range to which an output voltage of the first differential amplifier belongs from the reference voltage ranges obtained by the division, and coding lower bits in accordance with the obtained reference voltage ranges.

Claim 14

The two-step parallel A/D converter of claim 9, further comprising a fourth differential amplifier having the same gain as those of the first to third differential amplifiers and serving to amplify a median voltage of the reference voltage range obtained by the upper bit converting section on the basis of the same median voltage, an output voltage of the fourth differential amplifier being input, to the lower bit converting section, as a median reference voltage of a voltage range from the high level reference voltage to the low level reference voltage.

Claim 15

The two-step parallel A/D converter of claim 10, wherein the fourth differential amplifier has another output line than an output line for outputting a voltage to the lower bit converting section, the output line being connected to an output line of the first differential amplifier through a resistor.

Claim 16

The two-step parallel A/D converter of claim 9, further comprising switching means provided between the upper bit converting section and the first differential amplifier for switching, in accordance with a given control signal, a first state in which the median voltage of the reference voltage range obtained by the upper bit converting section is output as a reference voltage and the voltage of the analog signal is output as a voltage to be amplified to the first differential amplifier, and a second state in which the median voltage of the reference voltage range obtained by the upper bit converting section is output as the reference voltage and the voltage to be amplified to the first differential amplifier.

Claim 17

The two-step parallel A/D converter of claim 9, further comprising switching means provided between the upper bit converting section and the first differential amplifier for switching, in accordance with the given control signal, a first state in which the median voltage of the reference voltage range obtained by the upper bit converting section is output as a reference voltage and the voltage of the analog signal is output as a voltage to be amplified to the first differential amplifier, and a second state in which the voltage of the analog signal is output as the reference voltage and the voltage to be amplified to the first differential amplifier.

Claim 18

A two-step parallel A/D converter for performing A/D conversion of an input analog signal by upper bit conversion and lower bit conversion, comprising: an upper bit converting section for dividing a portion between a predetermined high level reference voltage and a predetermined low level reference voltage into a plurality of reference voltage ranges, obtaining a reference voltage range to which a voltage of the analog signal belongs from the reference voltage ranges obtained by the division, and coding upper bits according to the obtained reference voltage range; a first differential amplifier for amplifying the voltage of the analog signal on the basis of a median voltage of the reference voltage range obtained by the upper bit converting section; a second differential amplifier having the same gain as that of the first differential amplifier and serving to amplify an upper limit voltage of the reference voltage range selected from the reference voltage ranges obtained by the division in the upper bit converting section on the basis of the median voltage of the reference voltage range; a third differential amplifier having the same gain as those of the first and second differential amplifiers and serving to amplify a lower limit voltage of the reference voltage range selected from the reference voltage ranges obtained by the division in the upper bit converting section on the basis of the median voltage of the reference voltage range; and a lower bit converting section for setting an output voltage of the second differential amplifier to a high level reference voltage for lower bit conversion, setting an output voltage of the third differential amplifier to a low level reference voltage for lower bit conversion, dividing a portion between the high level reference voltage and the low level reference voltage into a plurality of reference voltage ranges, obtaining a reference voltage range to which an output voltage of the first differential amplifier belongs from the reference voltage ranges obtained by the division, and coding lower bits in accordance with the obtained reference voltage range.

Claim 19

A two-step parallel A/D converter for performing A/D conversion of an input analog signal by upper bit conversion and lower bit conversion, comprising: an upper bit converting section for dividing a portion between a predetermined high level reference voltage and a predetermined low level reference voltage into a plurality of reference voltage ranges, obtaining a reference voltage range to which a voltage of the analog signal belongs from the reference voltage ranges obtained by the division, and coding upper bits according to the obtained reference voltage range; a first differential amplifier for amplifying the voltage of the analog signal on the basis of a median voltage of the reference voltage range obtained by the upper bit converting section; a second differential amplifier having the same gain as that of the first differential amplifier and serving to amplify an upper limit voltage of the reference voltage range selected from the reference voltage ranges obtained by the division in the upper bit converting section on the basis of the median voltage of the reference voltage range; a third differential amplifier having the same gain as those of the first and second differential amplifiers and serving to amplify a lower limit voltage of the reference voltage range selected from the reference voltage ranges obtained by the division in the upper bit converting section on the basis of the median voltage of the reference voltage range; and a lower bit converting section for setting an output voltage of the second differential amplifier to a high level reference voltage for lower bit conversion, setting an output voltage of the third differential amplifier to a low level reference voltage for lower bit conversion, dividing a portion between the high level reference voltage and the low level reference voltage into a plurality of reference voltage ranges, obtaining a reference voltage range to which an output voltage of the first differential amplifier belongs from the reference voltage ranges obtained by the division, and coding lower bits in accordance with the obtained reference voltage range.

Claim 20

The two-step parallel A/D converter of claim 14, further comprising a fourth differential amplifier having the same gain as those of the first to third differential amplifiers and serving to amplify a median voltage of the reference voltage range selected from the reference voltage ranges obtained by the division in the upper bit converting section on the basis of the median voltage, an output voltage of the fourth differential amplifier being input, to the lower bit converting section, as a median reference voltage of the voltage range from the high level reference voltage to the low level reference voltage.

Claim 21

The two-step parallel A/D converter of claim 15, wherein the fourth differential amplifier has another output line than an output line for outputting a voltage to the lower bit converting section, the output line being connected to an output line of the first differential amplifier through a resistor.

Claim 22

The two-step parallel A/D converter of claim 14, further comprising switching means provided between the upper bit converting section and the first differential amplifier for switching, in accordance with a given control signal, a first state in which the median voltage of the reference voltage range obtained by the upper bit converting section is output as a reference voltage and the voltage of the analog signal is output as a voltage to be amplified to the first differential amplifier, and a second state in which the median voltage of the reference voltage range obtained by the upper bit converting section is output as the reference voltage and the voltage to be amplified to the first differential amplifier.

Claim 23

The two-step parallel A/D converter of claim 14, further comprising switching means provided between the upper bit converting section and the first differential amplifier for switching, in accordance with the given control signal, a first state in which the median voltage of the reference voltage range obtained by the upper bit converting section is output as a reference voltage to the first differential amplifier and the voltage of the analog signal is output as a voltage to be amplified to the first differential amplifier, and a second state in which the voltage of the analog signal is output as the reference voltage and the voltage to be amplified to the first differential amplifier.