Semiconductor fabrication employing a local interconnect

Abstract

Abstract An integrated circuit fabrication process is provided in which a sub-level local interconnect is formed between a gate conductor of one transistor and a junction of another transistor. The formation of a sub-level local interconnect allows for higher packing density by removing the local interconnect to a sub-level dielectrically spaced from possibly other local interconnects and from the distal interconnect normally associated with device interconnection. A semiconductor topography is provided which includes a first transistor laterally spaced from a second transistor, the transistors being arranged upon and within the substrate. An interlevel dielectric is deposited across the semiconductor topography. A portion of the interlevel dielectric is removed to form a trench. The trench is then filled with a conductive material to form a local interconnect extending horizontally above a portion of the first transistor and a portion of the second transistor. Portions of the interlevel dielectric and the local interconnect are removed in sequence while retaining the patterned masking layer. Removal of the local interconnect forms vias extending to the gate conductor of one transistor and to a junction of the other transistor, or from the gate conductor of one transistor to a junction of the same transistor. A conductive material may be deposited in these vias to form plugs therein. Further, a capping dielectric layer may be deposited upon the interlevel dielectric and contact regions may be formed which abut the plugs. Therefore, distal interconnect conductive layers may then be formed dielectrically above the local interconnect which are then electrically coupled to the local interconnect through the contact regions.

Inventors

• 👤 Mark I. Gardner
• 👤 Daniel Kadosh
• 👤 Thomas E. Spikes, Jr.

Bibliographic Details