US5498569A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Layered local interconnect compatible with integrated circuit ferroelectric capacitors
Assignee: Ramtron International Corp
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Filing: 1994-08-22
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Granted: 1996-03-12
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Expires: 2014-08-22
Abstract
Abstract A method of forming a local interconnect for a ferroelectric memory cell includes the steps of simultaneously opening top electrode and source/drain contacts to the ferroelectric memory cell, sputtering a first blanket metal layer comprised of platinum or palladium on a top surface of the ferroelectric memory cell, annealing the ferroelectric memory cell to simultaneously recover damage in a ferroelectric capacitor dielectric of the memory cell, and to silicidize the first metal layer in the source/drain contact, sputtering a second blanket metal layer comprised of titanium nitride on a top surface of the first metal layer, and selectively etching the first and second metal layers to form the local interconnect between the top electrode and source/drain contacts of the ferroelectric memory cell.
Inventors
- 👤 Brian Eastep
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 00:47
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
157 words
A method of forming a local interconnect for a partially processed ferroelectric memory cell, the method comprising the steps of: simultaneously opening top electrode and source/drain contacts to the ferroelectric memory cell; forming a first blanket metal layer comprised of platinum or palladium on a top surface of the ferroelectric memory cell; annealing the ferroelectric memory cell to simultaneously recover damage in a ferroelectric capacitor dielectric of the memory cell, and to silicidize the first metal layer in the source/drain contact, whereby a portion of the first metal layer that is silicidized in the source/drain contact becomes physically discontinuous with and electrically isolated from a remaining portion of the first metal layer; forming a second blanket metal layer comprised of titanium nitride on a top surface of the first metal layer; and selectively etching the first and second metal layers to form the local interconnect between the top electrode and source/drain contacts of the ferroelectric memory cell.
Claim 2
Independent Claim
157 words
A method of forming a local interconnect for a partially processed ferroelectric memory cell, the method comprising the steps of: simultaneously opening top electrode and source/drain contacts to the ferroelectric memory cell; forming a first blanket metal layer comprised of platinum or palladium on a top surface of the ferroelectric memory cell; annealing the ferroelectric memory cell to simultaneously recover damage in a ferroelectric capacitor dielectric of the memory cell, and to silicidize the first metal layer in the source/drain contact, whereby a portion of the first metal layer that is silicidized in the source/drain contact becomes physically discontinuous with and electrically isolated from a remaining portion of the first metal layer; forming a second blanket metal layer comprised of titanium nitride on a top surface of the first metal layer; and selectively etching the first and second metal layers to form the local interconnect between the top electrode and source/drain contacts of the ferroelectric memory cell.
Claim 3
Dependent Claim
30 words
The method of claim 1 in which the step of forming a first metal layer comprises the step of forming a first metal layer about 300 to 500 Angstroms thick.
Claim 4
Dependent Claim
28 words
The method of claim 1 in which the step of forming a first metal layer comprises the step of sputtering platinum or palladium in an argon ambient environment.
Claim 5
Dependent Claim
27 words
The method of claim 1 in which the annealing step comprises the step of annealing the ferroelectric memory cell at a temperature between 450° and 700° C.
Claim 6
Dependent Claim
21 words
The method of claim 1 in which the annealing step is performed for a duration of between 30 and 90 minutes.
Claim 7
Dependent Claim
17 words
The method of claim 1 in which the annealing step is performed in an oxygen ambient environment.
Claim 8
Dependent Claim
30 words
The method of claim 1 in which the step of forming a second metal layer comprises the step of forming a second metal layer about 500 to 1000 Angstroms thick.
Claim 9
Dependent Claim
26 words
The method of claim 1 in which the step of forming a second metal layer comprises the step of sputtering titanium in a nitrogen ambient environment.
Claim 10
Dependent Claim
54 words
The method of claim 1 in which the selective etching step comprises the steps of: applying a photoresist layer to the surface of the second metal layer; patterning the photoresist layer; and selectively etching the first and second metal layers during a single etching step according to a pattern established in the photoresist layer.
Claim 11
Dependent Claim
36 words
The method of claim 1 further comprising the step of controlling the thicknesses of the first and second metal layers so that the sheet resistance of the local interconnect is less than ten ohms per square.
Claim 12
Independent Claim
167 words
A method of forming a low resistivity interconnect between a first point and a second point of an integrated circuit ferroelectric memory, the method comprising the steps of: opening a contact to a silicon substrate between the first point and the second point; forming a first blanket metal layer comprised of platinum or palladium on a top surface of the ferroelectric memory; annealing the ferroelectric memory to simultaneously recover damage in a ferroelectric capacitor dielectric material used in the ferroelectric memory, and to silicidize the first metal layer in the contact, whereby a portion of the first metal layer that is silicidized in the contact becomes physically discontinuous with and electrically isolated from a remaining portion of the first metal layer; forming a second blanket metal layer comprised of titanium nitride on a top surface of the first metal layer; and selectively etching the first and second metal layers to form the low resistivity interconnect between the first point and the second point of the integrated circuit.
Claim 13
Independent Claim
167 words
A method of forming a low resistivity interconnect between a first point and a second point of an integrated circuit ferroelectric memory, the method comprising the steps of: opening a contact to a silicon substrate between the first point and the second point; forming a first blanket metal layer comprised of platinum or palladium on a top surface of the ferroelectric memory; annealing the ferroelectric memory to simultaneously recover damage in a ferroelectric capacitor dielectric material used in the ferroelectric memory, and to silicidize the first metal layer in the contact, whereby a portion of the first metal layer that is silicidized in the contact becomes physically discontinuous with and electrically isolated from a remaining portion of the first metal layer; forming a second blanket metal layer comprised of titanium nitride on a top surface of the first metal layer; and selectively etching the first and second metal layers to form the low resistivity interconnect between the first point and the second point of the integrated circuit.
Claim 14
Dependent Claim
37 words
The method of claim 11 in which the step of forming a first metal layer comprises the step of sputtering platinum or palladium in an argon ambient environment to a thickness of about 300 to 500 Angstroms.
Claim 15
Dependent Claim
40 words
The method of claim 11 in which the annealing step comprises the step of annealing the ferroelectric memory at a temperature between 450° and 700° C. for a duration of between 30 and 90 minutes in an oxygen ambient environment.
Claim 16
Dependent Claim
35 words
The method of claim 11 in which the step of forming a second metal layer comprises the step of sputtering titanium in a nitrogen ambient environment to a thickness of about 500 to 1000 Angstroms.
Claim 17
Dependent Claim
54 words
The method of claim 11 in which the selective etching step comprises the steps of: applying a photoresist layer to the surface of the second metal layer; patterning the photoresist layer; and selectively etching the first and second metal layers during a single etching step according to a pattern established in the photoresist layer.
Claim 18
Dependent Claim
41 words
The method of claim 11 further comprising the step of controlling the thicknesses of the first and second metal layers so that the sheet resistance of the low resistivity interconnect passing over silicidized silicon is less than two ohms per square.
Claim 19
Dependent Claim
190 words
A metallization method for an integrated circuit ferroelectric memory, the method comprising the steps of: simultaneously opening top electrode and source/drain contacts to a ferroelectric memory cell, and at least one separate substrate contact between two predetermined points in the memory; forming a first blanket metal layer comprised of platinum or palladium on a top surface of the ferroelectric memory; annealing the ferroelectric memory in an oxygen ambient environment to simultaneously recover damage in a ferroelectric capacitor dielectric material used in the ferroelectric memory, and to silicidize the first metal layer in the source/drain and substrate contacts, whereby a portion of the first metal layer that is silicidized in the source/drain and substrate contacts becomes physically discontinuous with and electrically isolated from a remaining portion of the first metal layer; forming a second blanket metal layer comprised of titanium nitride on a top surface of the first metal layer; and selectively etching the first and second metal layers to form a local interconnect between the top electrode and source/drain contacts of the ferroelectric memory cell, as well as a low resistivity interconnect between the two predetermined points in the memory.
Claim 20
Dependent Claim
190 words
A metallization method for an integrated circuit ferroelectric memory, the method comprising the steps of: simultaneously opening top electrode and source/drain contacts to a ferroelectric memory cell, and at least one separate substrate contact between two predetermined points in the memory; forming a first blanket metal layer comprised of platinum or palladium on a top surface of the ferroelectric memory; annealing the ferroelectric memory in an oxygen ambient environment to simultaneously recover damage in a ferroelectric capacitor dielectric material used in the ferroelectric memory, and to silicidize the first metal layer in the source/drain and substrate contacts, whereby a portion of the first metal layer that is silicidized in the source/drain and substrate contacts becomes physically discontinuous with and electrically isolated from a remaining portion of the first metal layer; forming a second blanket metal layer comprised of titanium nitride on a top surface of the first metal layer; and selectively etching the first and second metal layers to form a local interconnect between the top electrode and source/drain contacts of the ferroelectric memory cell, as well as a low resistivity interconnect between the two predetermined points in the memory.
Claim 21
Dependent Claim
35 words
The method of claim 17 in which the annealing step comprises the step of annealing the ferroelectric memory at a temperature between 450° and 700° C. for a duration of between 30 and 90 minutes.
Claim 22
Dependent Claim
54 words
The method of claim 17 in which the selective etching step comprises the steps of: applying a photoresist layer to the surface of the second metal layer; patterning the photoresist layer; and selectively etching the first and second metal layers during a single etching step according to a pattern established in the photoresist layer.
Claim 23
Dependent Claim
40 words
The method of claim 17 further comprising the step of controlling the thicknesses of the first and second metal layers so that the sheet resistance of the local interconnect and low resistivity interconnect is less than ten ohms per square.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-12 | 1999-09-11 | 2000-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-12 | 2003-09-11 | 2004-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-12 | 2007-09-11 | 2008-03-12 | $7700.00 | Window Closed / Lapsed |