US5712508A
Expired / Lapsed
US
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Strapping via for interconnecting integrated circuit structures
Assignee: Renesas Electronics America Inc
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Filing: 1995-12-05
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Granted: 1998-01-27
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Expires: 2015-12-05
Abstract
Abstract A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a "strapping" via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.
Inventors
- 👤 Chuen-Der Lien
- 👤 Kyle W. Terrill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:03
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/15; Y; Y10; Y10S; Y10S148/00; Y10S148/02; Y10S148/03; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
109 words
An integrated circuit structure comprising: a semiconductor substrate having a doped region that contains dopants of a first conductivity type; a patterned layer overlying the semiconductor substrate, wherein the patterned layer includes a conducting region adjacent the doped region; an insulating layer overlying the patterned layer, the insulating layer having an opening to a portion of the conducting region and a portion of the doped region; and a polysilicon layer having a first portion disposed in the opening to create an electrically conductive path from the conducting region to the doped region and a second portion which is undoped and forms a resistive element connected to said first portion.
Claim 2
Dependent Claim
109 words
An integrated circuit structure comprising: a semiconductor substrate having a doped region that contains dopants of a first conductivity type; a patterned layer overlying the semiconductor substrate, wherein the patterned layer includes a conducting region adjacent the doped region; an insulating layer overlying the patterned layer, the insulating layer having an opening to a portion of the conducting region and a portion of the doped region; and a polysilicon layer having a first portion disposed in the opening to create an electrically conductive path from the conducting region to the doped region and a second portion which is undoped and forms a resistive element connected to said first portion.
Claim 3
Dependent Claim
19 words
The structure of claim 1, wherein the portion disposed in the opening contains dopants of the first conductivity type.
Claim 4
Dependent Claim
25 words
The structure of claim 2, wherein the portion of polysilicon layer in the opening contains dopants diffused from the doped region and the conducting region.
Claim 5
Dependent Claim
12 words
The structure of claim 1, wherein the conducting region comprises doped polysilicon.
Claim 6
Dependent Claim
11 words
The structure of claim 1, wherein the conducting region comprises silicide.
Claim 7
Dependent Claim
139 words
An interconnect structure for a memory cell comprising: a semiconductor substrate which includes a doped region that forms a source/drain of a first transistor; a patterned layer overlying the semiconductor substrate, wherein the patterned layer includes a conducting region adjacent the doped region, wherein the conducting region forms a gate of a second transistor; an insulating layer overlying the patterned layer, the insulating layer having a single contiguous opening to a portion of the conducting region and a portion of the doped region; and a polysilicon region having a first portion disposed in the opening and on a top surface of the doped region and a second portion in the opening and on a top surface of the conducting region, wherein the first and second portions create an electrically conductive path from the conducting region to the doped region.
Claim 8
Dependent Claim
139 words
An interconnect structure for a memory cell comprising: a semiconductor substrate which includes a doped region that forms a source/drain of a first transistor; a patterned layer overlying the semiconductor substrate, wherein the patterned layer includes a conducting region adjacent the doped region, wherein the conducting region forms a gate of a second transistor; an insulating layer overlying the patterned layer, the insulating layer having a single contiguous opening to a portion of the conducting region and a portion of the doped region; and a polysilicon region having a first portion disposed in the opening and on a top surface of the doped region and a second portion in the opening and on a top surface of the conducting region, wherein the first and second portions create an electrically conductive path from the conducting region to the doped region.
Claim 9
Dependent Claim
23 words
The structure of claim 6, wherein the first and second portions of the polysilicon region are doped with the same conductivity type dopants.
Claim 10
Dependent Claim
29 words
The structure of claim 7, wherein the polysilicon region further comprises a third portion which is undoped and forms a resistive element connected to the portions in the opening.
Claim 11
Dependent Claim
28 words
The structure of claim 8, wherein the first, second, and third portions of the polysilicon layer constitute a cross-couple interconnect and a pull-up resistor for the memory cell.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-01-26 | 2001-07-28 | 2002-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-26 | 2005-07-28 | 2006-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-01-26 | 2009-07-28 | 2010-01-27 | $7700.00 | Window Closed / Lapsed |