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US5970341A
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Method for forming vertical channels in split-gate flash memory cell
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1997-12-11
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Granted: 1999-10-19
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Expires: 2017-12-11
Abstract
Abstract A method of forming a vertical memory split gate flash memory device on a silicon semiconductor substrate is provided by the following steps. Form a floating gate trench hole in the silicon semiconductor substrate, the trench hole having trench surfaces. Form a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. Form a floating gate electrode layer filling the trench hole on the outer surfaces of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode layer. Pattern the floating gate electrode layer by removing the gate electrode layer from the drain region side of the trench hole. Form a control gate hole therein. Form an interelectrode dielectric layer over the top surface of the floating gate electrode, and over the tunnel oxide layer. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode and extending down into the control gate hole in the trench hole.
Inventors
- 👤 Chrong-Jung Lin
- 👤 Chia-Ta Hsieh
- 👤 Jong Chen
- 👤 Di-Son Kuo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:08
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D30/6891; H10D30/6894; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
164 words
A method of forming a vertical memory split gate flash memory device on a silicon semiconductor substrate comprising: forming a floating gate trench hole in said silicon semiconductor substrate, said trench hole having trench surfaces, forming a tunnel oxide layer on said trench surfaces, said tunnel oxide layer having outer surfaces, forming a floating gate electrode layer filling said trench hole on said outer surfaces of said tunnel oxide layer, forming source/drain regions in said substrate self-aligned with said floating gate electrode layer, patterning said floating gate electrode layer by removing said gate electrode layer from said drain region side of said trench hole forming a control gate hole therein, forming an interelectrode dielectric layer over the top surface of said floating gate electrode layer, and over said tunnel oxide layer, and forming a control gate electrode over said interelectrode dielectric layer over the top surface of said floating gate electrode layer and extending down into said control gate hole in said trench hole.
Claim 2
Independent Claim
164 words
A method of forming a vertical memory split gate flash memory device on a silicon semiconductor substrate comprising: forming a floating gate trench hole in said silicon semiconductor substrate, said trench hole having trench surfaces, forming a tunnel oxide layer on said trench surfaces, said tunnel oxide layer having outer surfaces, forming a floating gate electrode layer filling said trench hole on said outer surfaces of said tunnel oxide layer, forming source/drain regions in said substrate self-aligned with said floating gate electrode layer, patterning said floating gate electrode layer by removing said gate electrode layer from said drain region side of said trench hole forming a control gate hole therein, forming an interelectrode dielectric layer over the top surface of said floating gate electrode layer, and over said tunnel oxide layer, and forming a control gate electrode over said interelectrode dielectric layer over the top surface of said floating gate electrode layer and extending down into said control gate hole in said trench hole.
Claim 3
Dependent Claim
27 words
A method of forming a memory device in accordance with claim 1 wherein: said trench hole has a depth from about 3,000 Å to about 8,000 Å.
Claim 4
Dependent Claim
46 words
A method of forming a memory device in accordance with claim 1 wherein: said tunnel oxide layer has a thickness from about 70 Å to about 150 Å, and said floating gate electrode layer has a thickness of from about 500 Å to about 2,000 Å.
Claim 5
Dependent Claim
58 words
A method of forming a memory device in accordance with claim 1 wherein: said source/drain implant comprises ions selected from the group comprising arsenic and phosphorus ions implanted with a concentration of dopant from about 5 E 19 atoms/cm 3 to about 1 E 20 atoms/cm 3 at an energy from about 25 keV to about 50 keV.
Claim 6
Dependent Claim
84 words
A method of forming a memory device in accordance with claim 1 wherein: said tunnel oxide layer has a thickness from about 70 Å to about 150 Å, and said floating gate electrode layer has a thickness of from about 500 Å to about 2,000 Å, and source/drain regions were ion implanted with atoms selected from the group consisting of arsenic and phosphorus ions with a concentration of dopant from about 5 E 19 atoms/cm 3 to about 5 E 20 atoms/cm 3 .
Claim 7
Dependent Claim
30 words
A method of forming a memory device in accordance with claim 1 wherein: said floating gate electrode layer comprises doped polysilicon from about 500 Å to about 2,000 Å thick.
Claim 8
Dependent Claim
74 words
A method of forming a memory device in accordance with claim 1 wherein: a source line region and a drain line region are formed on opposite sides of said trench hole, said source line region is provided on the source side of said trench hole aligned with and adjacent to said source region, said drain line region is provided on the drain side of said trench hole aligned with and over said drain region.
Claim 9
Dependent Claim
58 words
A method of forming a memory device in accordance with claim 7 wherein: said source line region and said drain line region were doped with an N-type dopant selected from the group consisting of arsenic and phosphorus ions with a concentration of dopant from about 5 E 19 atoms/cm 3 to about 1 E 20 atoms/cm 3 .
Claim 10
Dependent Claim
32 words
A method of forming a memory device in accordance with claim 8 wherein: said floating gate electrode layer comprises doped polysilicon with a thickness from about 500 Å to about 2,000 Å.
Claim 11
Dependent Claim
66 words
A method of forming a memory device in accordance with claim 1 wherein the following memory cell operation conditions obtain: ______________________________________
Prog. Erase Read
______________________________________
BIT LINE Sel. V.sub.cc Floating
V.sub.cc
(DRAIN) Unsel. 0 0 0
WORD LINE Sel. V.sub.cc (-V.sub.pp)
V.sub.cc
(GATE) Unsel. 0 0 0
SOURCE Sel. V.sub.pp V.sub.cc
0
Unsel. 0 0 0
BULK Sel. 0 0 0
Unsel. 0 0 0.
______________________________________
Claim 12
Dependent Claim
31 words
A method of forming a memory device in accordance with claim 9 wherein: said control gate electrode comprises doped polysilicon with a thickness from about 1,000 Å to about 2,500 Å.
References Cited (Backward Citations)
US5162247A
Cited
US5045490A
Cited
US5049515A
Cited
US5180680A
Cited
US5460989A
Cited
US5313421A
Cited
US5467305A
Cited
US5468663A
Cited
US5595927A
Cited
US5786612A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-18 | 2003-04-19 | 2003-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-18 | 2007-04-19 | 2007-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-18 | 2011-04-19 | 2011-10-19 | $7700.00 | Window Closed / Lapsed |