Plated copper interconnect structure

Claim 2

A semiconductor device comprising: a semiconductor substrate; a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises: a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, platinum, rhodium or copper deposited in the opening; and a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening.

Claim 3

The semiconductor device according to claim 1, wherein the interconnect pattern comprises copper plated on the seed layer.

Claim 4

A semiconductor device comprising: a semiconductor substrate; a dielectric interlayer formed ona level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therin filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises: a seed layer comprising an alloy containing about 0.5 at. % to about 99.5 at. % copper and a refractory metal; and a copper or copper-base alloy electroplated or electroless plated on the seed layer in the opening.

Claim 5

A semiconductor device comprising: a semiconductor substrate; a dielectric interlayer formed ona level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therin filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises: a seed layer comprising an alloy containing about 0.5 at. % to about 99.5 at. % copper and a refractory metal; and a copper or copper-base alloy electroplated or electroless plated on the seed layer in the opening.

Claim 6

The semiconductor device according to claim 3, wherein the refractory metal comprises tantalum or tungsten.

Claim 7

The semiconductor device according to claim 4, wherein the refractory metal comprises tantalum.

Claim 8

The semiconductor device according to claim 3, wherein the interconnect pattern further comprises a barrier layer containing a refractory metal, alloy or compound thereof, formed in the opening and on the upper surface of the dielectric interlayer, and the seed layer is formed on the barrier layer.

Claim 9

The semiconductor device according to claim 6, wherein the barrier layer comprises tantalum, tungsten or a nitride thereof.

Claim 10

The semiconductor device according to claim 3, wherein the interconnect pattern comprises one or more filled openings forming a conductive plug in a contact or via opening and/or a conductive line in a trench opening.

Claim 11

The semiconductor device according to claim 8, wherein the contact or via and trench opening has an aspect ratio of about 2:1 or greater.

Claim 12

A semiconductor device comprising: a semiconductor substrate; a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises: a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper deposited in the opening; and a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening, further comprising a silicon nitride barrier layer formed on the electroless plated or electroplated copper or copper-base alloy.

Claim 13

A semiconductor device comprising: a semiconductor substrate; a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises: a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper deposited in the opening; and a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening, further comprising a silicon nitride barrier layer formed on the electroless plated or electroplated copper or copper-base alloy.

Claim 14

A semiconductor device comprising: a semiconductor substrate; a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises: a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper deposited in the opening; and a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening, further comprising an etch stop layer on the upper surface of the dielectric interlayer.

Claim 15

A semiconductor device comprising: a semiconductor substrate; a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises: a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper deposited in the opening; and a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening, further comprising an etch stop layer on the upper surface of the dielectric interlayer.

Claim 18

The method according to claim 12, comprising electroplating or electroless plating of copper on the seed layer.

Claim 19

The method according to claim 12, comprising sputter depositing the seed layer.

Claim 22

The method according to claim 15, wherein the refractory metal comprises tantalum.

Claim 25

The method according to claim 17, wherein the barrier layer comprises tantalum, tungsten or a nitride thereof.

Claim 26

The method according to claim 15, comprising forming one or more openings in the dielectric interlayer and filling each opening to form a conductive plug in a contact or via opening and/or a conductive line in a trench opening.

Claim 27

The method according to claim 19, wherein the contact or via and trench opening has an aspect ratio of about 2:1 or greater.

Claim 30

The method according to claim 15, further comprising planarizing to remove the copper or copper-base alloy layer and seed layer from the upper surface of the dielectric interlayer.

Claim 33

The method according to claim 19, wherein at least one opening comprises a contact or via opening, which method further comprises: electroplating or electroless plating of copper or a copper-base alloy to form a conductive plug; planarizing; depositing another dielectric interlayer having an upper surface; forming a trench opening in said another dielectric interlayer communicating with the conductive plug; depositing a seed layer, comprising an alloy of a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper, in the trench opening and on the upper surface of said another dielectric interlayer; and filling the trench opening to form a conductive line by electroplating or electroless plating of copper or a copper-base alloy on the seed layer to form a conductive line in electrical contact with the conductive plug.

Claim 34

The method according to claim 19, comprising: forming an opening comprising a lower contact or via opening section in communication with an upper trench opening section by a damascene technique; depositing a seed layer, comprising an alloy of a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper, in the opening; and filling the opening by electroplating or electroless plating of copper or a copper-base alloy on the seed layer to simultaneously form a conductive line in the upper trench opening section in electrical contact with a conductive plug in the lower contact or via opening section.

Claim 35

A semiconductor device comprising: a semiconductor substrate; a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises a multilayer structure comprising: (a) a layer of a refractory metal having an upper surface; (b) an intermediate layer comprising the refractory metal and one or more elements selected from the group consisting of Ni, Co, Ag, Au, Pd, Pt, Rh and Cu, wherein the concentration of the refractory metal decreases across the intermediate layer from the upper surface of the refractory metal layer from 100% to 0% and the concentration of one or more of Ni, Co, Ag, Au, Pd, Pt, Rh or Cu increases from 0% to 100% from the upper surface of the intermediate layer; and (c) a layer containing one or more Ni, Co, Ag, Au, Pd, Pt, Rh or Cu.

Claim 36

A semiconductor device comprising: a semiconductor substrate; a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises a multilayer structure comprising: (a) a layer of a refractory metal having an upper surface; (b) an intermediate layer comprising the refractory metal and one or more elements selected from the group consisting of Ni, Co, Ag, Au, Pd, Pt, Rh and Cu, wherein the concentration of the refractory metal decreases across the intermediate layer from the upper surface of the refractory metal layer from 100% to 0% and the concentration of one or more of Ni, Co, Ag, Au, Pd, Pt, Rh or Cu increases from 0% to 100% from the upper surface of the intermediate layer; and (c) a layer containing one or more Ni, Co, Ag, Au, Pd, Pt, Rh or Cu.

Claim 37

The semiconductor device according to claim 26, wherein the interconnection pattern further comprises copper or a copper alloy electroplated or electroless plated on the multi-layer structure.

Claim 38

The semiconductor device according to claim 24, wherein the interconnect pattern further comprises a barrier layer under the multi-layer structure.

Claim 39

The semiconductor device according to claim 24, wherein the seed layer comprises an alloy of tantalum or tungsten with copper.

Claim 40

A semiconductor device comprising: a semiconductor substrate; a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises: a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper deposited in the opening; and a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening, wherein the dielectric interlayer comprises an oxide.

Claim 41

A semiconductor device comprising: a semiconductor substrate; a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises: a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper deposited in the opening; and a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening, wherein the dielectric interlayer comprises an oxide.

Claim 42

The semiconductor device according to claim 30, wherein the oxide comprises silicon dioxide.

Claim 45

The method according to claim 32, wherein the oxide comprises silicon dioxide.

Claim 46

A semiconductor device comprising: a semiconductor substrate; a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises: a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper deposited in the opening; and a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening, wherein the copper or copper-based alloy is electroplated or electroless plated directly on the seed layer in the opening.

Claim 47

A semiconductor device comprising: a semiconductor substrate; a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises: a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper deposited in the opening; and a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening, wherein the copper or copper-based alloy is electroplated or electroless plated directly on the seed layer in the opening.

Claim 50

A semiconductor device comprising: a semiconductor substrate; a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises: a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper deposited in the opening; and a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening, wherein the refractory metal comprises tantalum or tungsten.

Claim 51

A semiconductor device comprising: a semiconductor substrate; a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises: a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper deposited in the opening; and a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening, wherein the refractory metal comprises tantalum or tungsten.