US5288951A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Copper-based metallizations for hybrid integrated circuits
Assignee: Nokia Bell Labs
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Filing: 1992-10-30
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Granted: 1994-02-22
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Expires: 2012-10-30
Abstract
Abstract A new metanization is described which is a composite of subsequent metal layers beginning with a layer of titanium and having in an ascending order the following composition: Ti - TiPd - Cu - Ni - Au. TiPd is an alloy of titanium and palladium containing from 0.3 to 14 weight percent Pd, by the weight of the alloy. The TiPd alloy is etchable in an aqueous BF solution containing from 0.5 to 2.0 and higher, preferably from 0.5 to 1.2 weight percent BF. The use of the TiPd alloy avoids the occurrence of Pd residues remaining after the etching of Ti layer and liftoff (rejection etching) of Pd layer in a prior art Ti-Pd-Cu-Ni-Au metanization. Ti and TiPd layers are present in a thickness ranging from 100 to 300 nm and from 50 to 300 nm, respectively, and in a total minimum thickness needed to maintain bonding characteristics of the metallization. The metallization is suitable for use in various circuits including integrated circuits (ICs), hybrid integrated circuits (HICs), film integrated circuits (FICs), multi-chip modules (MCMs), etc.
Inventors
- 👤 Robert P. Frankenthal
- 👤 Ajibola O. Ibidunni
- 👤 Dennis L. Krause
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:51
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/22; H05K3/24; H05K3/244; H10; H10P; H10P50/00; C; C23; C23C; C23C28/00; C23C28/02; C23C28/021; C25; C25D; C25D5/00; C25D5/02; C25D5/022; C25D5/10; C25D5/12; H05K3/10; H05K3/108; H05K3/38; H05K3/388; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/66; H05K2203/00; H05K2203/07; H05K2203/0703; H05K2203/0723; H05K3/02; H05K3/06; H05K3/061; H05K3/062; H05K3/243
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
103 words
A circuit including thin film elements and electrical interconnections on a major surface of an insulating substrate, said interconnections comprising: a first metal layer comprising titanium formed on said substrate; a second metal layer comprising an alloy of titanium and palladium formed on said first metal layer, said alloy comprising 0.3 to 14 weight percent palladium based on the weight of the alloy; a third metal layer comprising copper formed on said second metal layer, a fourth metal layer comprising nickel formed on said third metal layer; a fifth metal layer comprising gold formed on at least portions of said fourth metal layer.
Claim 2
Dependent Claim
103 words
A circuit including thin film elements and electrical interconnections on a major surface of an insulating substrate, said interconnections comprising: a first metal layer comprising titanium formed on said substrate; a second metal layer comprising an alloy of titanium and palladium formed on said first metal layer, said alloy comprising 0.3 to 14 weight percent palladium based on the weight of the alloy; a third metal layer comprising copper formed on said second metal layer, a fourth metal layer comprising nickel formed on said third metal layer; a fifth metal layer comprising gold formed on at least portions of said fourth metal layer.
Claim 3
Dependent Claim
72 words
The circuit according to claim 1 wherein said first metal layer has a thickness within the range 100 to 300 nm, said second metal layer has a thickness within the range 50 to 300 nm, said third metal layer has a thickness within the range 2,500-4,000 nm, said fourth metal layer has a thickness within the range 800-2,000 nm, and said fifth metal layer has a thickness within the range 700-2,500 nm.
Claim 4
Dependent Claim
23 words
The circuit according to claim 1 wherein the fifth metal layer is tonned on substantially the entire surface of said fourth metal layer.
Claim 5
Dependent Claim
29 words
The circuit according to claim 1 wherein the fifth metal layer is formed only on the portions of said fourth metal layer which comprise bonding pads for said circuit.
Claim 6
Dependent Claim
143 words
A circuit including thin film elements and electrical interconnections on a major surface of an insulating substrate, said interconnections comprising: a first metal layer comprising titanium with a thickness in the range 100-300 nm formed on said substrate; a second metal layer comprising an alloy of titanium and palladium with thickness in the range 50-300 nm formed on said first metal layer, said alloy comprising palladium in an amount of from 0.3 to 14 weight percent of the alloy; a third metal layer comprising copper with a thickness in the range 2,500-4,000 nm formed over said second metal layer; a fourth metal layer comprising nickel with a thickness in the range 800-2,000 nm formed on said second layer; and a fifth metal layer comprising gold with a thickness in the range 700-2,500 nm formed on at least portions of said fourth metal layer.
Claim 7
Dependent Claim
143 words
A circuit including thin film elements and electrical interconnections on a major surface of an insulating substrate, said interconnections comprising: a first metal layer comprising titanium with a thickness in the range 100-300 nm formed on said substrate; a second metal layer comprising an alloy of titanium and palladium with thickness in the range 50-300 nm formed on said first metal layer, said alloy comprising palladium in an amount of from 0.3 to 14 weight percent of the alloy; a third metal layer comprising copper with a thickness in the range 2,500-4,000 nm formed over said second metal layer; a fourth metal layer comprising nickel with a thickness in the range 800-2,000 nm formed on said second layer; and a fifth metal layer comprising gold with a thickness in the range 700-2,500 nm formed on at least portions of said fourth metal layer.
Claim 8
Dependent Claim
21 words
The circuit according to claim 5 wherein the fifth layer is formed on substantially the entire surface of said fourth layer.
Claim 9
Dependent Claim
27 words
The circuit according to claim 1 wherein the fifth layer is formed only on those portions of said fourth layer which comprise bonding pads for said circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-02-21 | 1997-08-23 | 1998-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-21 | 2001-08-23 | 2002-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-21 | 2005-08-23 | 2006-02-22 | $7700.00 | Window Closed / Lapsed |