Microprocessor configured to route instructions of a second instruction set to a second execute unit in response to an escape instruction

Claim 2

A microprocessor comprising: an instruction cache configured to store a plurality of instructions, wherein said plurality of instructions includes instructions from a first instruction set and instructions from a second instruction set; an instruction decode unit coupled to receive said plurality of instructions from said instruction cache; one or more first execution units operable to execute said instructions from said first instruction set; a second execution unit operable to execute said instructions from said second instruction set; wherein said instruction decode unit is configured to dispatch said instructions from said first instruction set to said one or more first execution units, to detect an escape instruction in said plurality of instructions, and in response to a value encoded in said escape instruction to dispatch a plurality of subsequent instructions from the second instruction set to said second execution unit, wherein a total number of said subsequent instructions from said second instruction set dispatched to said second execution unit is dependent on said value encoded in said escape instruction, wherein said instruction decode unit is further configured to resume dispatch of said instructions from said first instruction set to said one or more first execution units in response to completion of said dispatching of said total number of said subsequent instructions to said second execution unit; wherein said instruction decode unit includes: one or more decoder circuits, wherein said one or more decoder circuits are coupled to receive said plurality of instructions, and configured to decode said instructions from said first instruction set, and dispatch said instructions from said first instruction set to said one or more first execution units; an escape decoder unit coupled to said one or more decoder circuits, wherein said escape decoder unit is coupled to receive said plurality of instructions concurrently with said one or more decoder circuits, wherein said escape decoder unit is configured to detect said escape instruction, and dispatch said subsequent instructions from said second instruction set to said second execution unit in response to said detection of said escape instruction; wherein said escape decoder unit includes a count register, wherein said count register is configured to store a value indicative of a remaining number of said subsequent instructions from said second instruction set to be dispatched to said second execute unit, wherein said escape decoder unit loads said count register with said total number in response to said detection of said escape instruction, wherein said escape decoder unit decrements said count register upon dispatching each of said subsequent instructions from said second instruction set to said second execution unit.

Claim 3

The microprocessor as recited in claim 1 wherein said escape decoder unit is configured to disable selected ones of said one or more decoder circuits from dispatching said subsequent instructions from said second instruction set to said one or more first execution units in response to said detection of said escape instruction.

Claim 4

The microprocessor as recited in claim 2 wherein each of said one or more decoder circuits is configured to receive an instruction of said plurality of instructions in a single clock cycle.

Claim 5

The microprocessor as recited in claim 3 wherein said escape decoder unit is configured to disable decoder circuits which receive said escape instruction or any of said subsequent instructions during a first clock cycle in which said escape instruction is detected.

Claim 6

The microprocessor as recited in claim 1 wherein said second execution unit comprises a digital signal processing unit.

Claim 9

The method as recited in claim 6 wherein said second execution unit comprises a digital signal processing unit configured within said microprocessor.

Claim 10

The method as recited in claim 6 wherein said second execution unit comprises a digital signal processor residing external to said microprocessor.

Claim 11

The method of claim 6, wherein said decoding of said plurality of instructions further comprises: said escape decoder unit disabling selected ones of said one or more decoder circuits from dispatching said subsequent instructions from said second instruction set to said one or more first execution units in response to said detection of said escape instruction; each of said one or more decoder circuits which receiving an instruction of said plurality of instructions in a single clock cycle; said escape decoder unit disabling decoder circuits which receive said escape instruction or instructions subsequent to said escape instruction in program order during a first clock cycle in which said escape instruction is detected; said escape decoder unit disabling all decoder circuits during clock cycles after said first clock cycle until said value in said count register attains a magnitude smaller than the number of said one or more decoder circuits.

Claim 12

A microprocessor comprising: an instruction cache configured to store a plurality of instructions, wherein said plurality of instructions includes instructions from a first instruction set and instructions from a second instruction set; an instruction decode it coupled to receive said plurality of instructions from said instruction cache; one or more first execution units operable to execute said instructions from said first instruction set; and a second execution unit operable to execute said instructions from said second instruction set; wherein said instruction decode unit is configured to dispatch said instructions from said first instruction set to said one or more first execution units, to detect an escape instruction in said plurality of instructions, and to dispatch a first number of subsequent instructions from said second instruction set to said second execution unit in response to said detection of said escape instruction, wherein said first number of subsequent instructions dispatched to said second execution unit is dependent upon a value specified by said escape instruction, wherein said instruction decode unit is further configured to resume dispatch of said instructions from said first instruction set to said one or more first execution units in response to completion of said dispatching of said first number of subsequent instructions to said second execution unit; wherein said instruction decode unit includes: one or more decoder circuits, wherein said one or more decoder circuits are coupled to receive said plurality of instructions, and configured to decode said instructions from said first instruction set, and dispatch said instructions from said first instruction set to said one or more first execution units; an escape decoder unit coupled to said one or more decoder circuits, wherein said escape decoder unit is coupled to receive said plurality of instructions concurrently with said one or more decoder circuits, wherein said escape decoder unit is configured to detect said escape instruction, and dispatch said first number of subsequent instructions from said second instruction set to said second execution unit in response to said detection of said escape instruction; wherein said escape decoder unit includes a count register, wherein said count register is configured to store a value indicative of a remaining number of said subsequent instructions from said second instruction set to be dispatched to said second execution unit, wherein said escape decoder unit loads said count register with said first number in response to said detection of said escape instruction, wherein said escape decoder unit decrements said counter register upon dispatching said subsequent instructions from said second instruction set to said second execution unit; wherein said escape decoder unit is configured to disable selected ones of said one or more decoder circuits from dispatching said subsequent instructions from said second instruction set to said one or more execution units in response to said detection of said escape instruction; wherein each of said one or more decoder circuits is configured to receive an instruction of said plurality of instructions in a single clock cycle; wherein said escape decoder unit is configured to disable decoder circuits which receive said escape instruction or instructions subsequent to said escape instruction in program order during a first clock cycle in which said escape instruction is detected; wherein said escape decoder unit is configured to disable all decoder circuits during clock cycles after said first clock cycle until said value in said count register attains a magnitude smaller than the number of said one or more decoder circuits.

Claim 13

A microprocessor comprising: an instruction cache configured to store a plurality of instructions, wherein said plurality of instructions includes instructions from a first instruction set and instructions from a second instruction set; an instruction decode it coupled to receive said plurality of instructions from said instruction cache; one or more first execution units operable to execute said instructions from said first instruction set; and a second execution unit operable to execute said instructions from said second instruction set; wherein said instruction decode unit is configured to dispatch said instructions from said first instruction set to said one or more first execution units, to detect an escape instruction in said plurality of instructions, and to dispatch a first number of subsequent instructions from said second instruction set to said second execution unit in response to said detection of said escape instruction, wherein said first number of subsequent instructions dispatched to said second execution unit is dependent upon a value specified by said escape instruction, wherein said instruction decode unit is further configured to resume dispatch of said instructions from said first instruction set to said one or more first execution units in response to completion of said dispatching of said first number of subsequent instructions to said second execution unit; wherein said instruction decode unit includes: one or more decoder circuits, wherein said one or more decoder circuits are coupled to receive said plurality of instructions, and configured to decode said instructions from said first instruction set, and dispatch said instructions from said first instruction set to said one or more first execution units; an escape decoder unit coupled to said one or more decoder circuits, wherein said escape decoder unit is coupled to receive said plurality of instructions concurrently with said one or more decoder circuits, wherein said escape decoder unit is configured to detect said escape instruction, and dispatch said first number of subsequent instructions from said second instruction set to said second execution unit in response to said detection of said escape instruction; wherein said escape decoder unit includes a count register, wherein said count register is configured to store a value indicative of a remaining number of said subsequent instructions from said second instruction set to be dispatched to said second execution unit, wherein said escape decoder unit loads said count register with said first number in response to said detection of said escape instruction, wherein said escape decoder unit decrements said counter register upon dispatching said subsequent instructions from said second instruction set to said second execution unit; wherein said escape decoder unit is configured to disable selected ones of said one or more decoder circuits from dispatching said subsequent instructions from said second instruction set to said one or more execution units in response to said detection of said escape instruction; wherein each of said one or more decoder circuits is configured to receive an instruction of said plurality of instructions in a single clock cycle; wherein said escape decoder unit is configured to disable decoder circuits which receive said escape instruction or instructions subsequent to said escape instruction in program order during a first clock cycle in which said escape instruction is detected; wherein said escape decoder unit is configured to disable all decoder circuits during clock cycles after said first clock cycle until said value in said count register attains a magnitude smaller than the number of said one or more decoder circuits.

Claim 14

The microprocessor as recited in claim 10 wherein said escape decoder unit is configured to enable decoder circuits which receive instructions following said first number of subsequent instructions from said second instruction set.