Programmable controller ("PC") with co-processing architecture

Claim 2

A co-processing system comprising: a first processor having a first instruction set for executing a first class of instructions including a first special instruction subset; a second processor having a second instruction set for executing a second class of instructions including a second special instruction subset; memory means for storing program instructions including instructions belonging to said first and second classes; first means, associated with said first processor, for fetching instructions from said memory means during operation of said first processor for execution by said first processor; second means, associated with said second processor, for fetching instructions from said memory means during operation of said second processor for execution by said second processor; first control passing means, associated with said first processor, for suspending the operation of said first processor and commencing the operation of said second processor when said first processor encounters an instruction in said first special instruction subset; and second control passing means, associated with said second processor, for suspending operation of said second processor and commencing operation of said first processor when said second processor encounters an instruction in said second special instruction subset.

Claim 3

The invention of Claim 1 wherein said first processor is a numeric processor and said second processor is an I/O processor.

Claim 4

3 . The invention of Claim 1 wherein said first processor is a numeric processor and said second processor is a Boolean processor.

Claim 5

The invention of Claim 1 wherein said first control passing means operates to suspend operation of said first processor part way through the execution by said first processor of the encountered instruction in said first special instruction subset.

Claim 6

The invention of Claim 1 wherein said first special instruction subset includes a memory-mapped access instruction having an address operand lying within a specified range; said first control passing means operates to suspend operation of said first processor by preventing completion of said memory-mapped access instruction; and said second control passing means operates to allow said first processor to complete said memory-mapped access instruction.

Claim 7

The invention of Claim 5 wherein: said memory-mapped access instruction is a jump indirect; and said second control passing means supplies a target address to allow completion of the jump.

Claim 8

A programmable controller comprising: a numeric processor having a first instruction set for executing a first class of instructions including a first special instruction subset; a Boolean processor having a second instruction set for executing a second class of instructions including a second special instruction subset including subroutine calls; memory means for storing program instructions including instructions belonging to said first and second classes; first means, associated with said numeric processor, for fetching instructions from said memory means during operation of said numeric processor for execution by said numeric processor; second means, associated with said Boolean processor, for fetching instructions from said memory means during operation of said Boolean processor for execution by said Boolean processor; first control passing means, associated with said numerical processor, for suspending the operation of said numeric processor and commencing the operation of said Boolean processor when said numeric processor encounters an instruction in said first special instruction subset; and second control passing means, associated with said Boolean processor, for suspending operation of said Boolean processor and commencing operation of said numeric processor when said Boolean processor encounters an instruction in said second special instruction subset.

Claim 9

A programmable controller comprising: a numeric processor having a first instruction set for executing a first class of instructions including a first special instruction subset; a Boolean processor having a second instruction set for executing a second class of instructions including a second special instruction subset including subroutine calls; memory means for storing program instructions including instructions belonging to said first and second classes; first means, associated with said numeric processor, for fetching instructions from said memory means during operation of said numeric processor for execution by said numeric processor; second means, associated with said Boolean processor, for fetching instructions from said memory means during operation of said Boolean processor for execution by said Boolean processor; first control passing means, associated with said numerical processor, for suspending the operation of said numeric processor and commencing the operation of said Boolean processor when said numeric processor encounters an instruction in said first special instruction subset; and second control passing means, associated with said Boolean processor, for suspending operation of said Boolean processor and commencing operation of said numeric processor when said Boolean processor encounters an instruction in said second special instruction subset.

Claim 10

The invention of Claim 7 wherein said first special instruction subset includes a memory reference to a location having an address within a specified range.

Claim 11

The invention of Claim 7 wherein: said first special instruction subset includes an indirect branch specifying a destination stored in a location having an address within a specified range; said first control passing means operates to signify that the contents of the addressed location are not yet available, thereby suspending operation of said first processor; and said second control passing means operates in conjunction with said second processor to provide a data operand specifying a destination address so that said first processor may complete the branch, thereby effecting passage of control to said first processor with said first processor beginning execution at the location specified.

Claim 12

A programmable controller comprising: a numeric processor having a first instruction set including a subset of native memory access instructions and a subset of native I/O instructions, said numeric processor having a READY input, adapted to receive signals signifying the completion of a memory or I/O access; a Boolean processor having a second instruction set including a subset of special BP instructions; an I/O processor having a third instruction set including a subset of special IOP instructions; memory means for storing program instructions including instructions belonging to said first, second, and third sets; first means, associated with said numeric processor, for fetching instructions from said memory means during operation of said numeric processor; second means, associated with said Boolean processor, for fetching instructions from said memory means during operation of said Boolean processor; third means, associated with said I/O processor, for fetching instructions from said memory means during operation of said I/O processor; NP/BP control passing means, responsive to said numeric processor's encountering a native memory access instruction referring to a location having an address within a specified range, for applying a false signal at said READY input, thereby suspending the operation of said numeric processor, and for commencing the operation of said Boolean processor; BP/NP control passing means, responsive to said Boolean processor's encountering a special BP instruction, for suspending the operation of said Boolean processor, and for commencing the operation of said numeric processor by constructing the operand sought by said numeric processor and applying a true signal at said READY input; NP/IOP control passing means, responsive to said numeric processor's encountering a native I/O instruction, for applying a false signal at said READY input, thereby suspending the operation of said numeric processor, and for commencing the operation of said I/O processor; and IOP/NP control passing means, responsive to said I/O processor's encountering a special IOP instruction, for suspending operation of said I/O processor, and for commencing operation of said numeric processor by applying a true signal at said READY input.

Claim 13

A programmable controller comprising: a numeric processor having a first instruction set including a subset of native memory access instructions and a subset of native I/O instructions, said numeric processor having a READY input, adapted to receive signals signifying the completion of a memory or I/O access; a Boolean processor having a second instruction set including a subset of special BP instructions; an I/O processor having a third instruction set including a subset of special IOP instructions; memory means for storing program instructions including instructions belonging to said first, second, and third sets; first means, associated with said numeric processor, for fetching instructions from said memory means during operation of said numeric processor; second means, associated with said Boolean processor, for fetching instructions from said memory means during operation of said Boolean processor; third means, associated with said I/O processor, for fetching instructions from said memory means during operation of said I/O processor; NP/BP control passing means, responsive to said numeric processor's encountering a native memory access instruction referring to a location having an address within a specified range, for applying a false signal at said READY input, thereby suspending the operation of said numeric processor, and for commencing the operation of said Boolean processor; BP/NP control passing means, responsive to said Boolean processor's encountering a special BP instruction, for suspending the operation of said Boolean processor, and for commencing the operation of said numeric processor by constructing the operand sought by said numeric processor and applying a true signal at said READY input; NP/IOP control passing means, responsive to said numeric processor's encountering a native I/O instruction, for applying a false signal at said READY input, thereby suspending the operation of said numeric processor, and for commencing the operation of said I/O processor; and IOP/NP control passing means, responsive to said I/O processor's encountering a special IOP instruction, for suspending operation of said I/O processor, and for commencing operation of said numeric processor by applying a true signal at said READY input.

Claim 14

The invention of Claim 10 wherein: said native memory access instruction to which said NP/BP control passing means is responsive is a branch with a level of indirection; and said operand is the location at which said numeric processor is to commence operation when control passes from said Boolean processor to said numeric processor.

Claim 15

The invention of Claim 10 wherein said operand contains compile-time information and run-time information.

Claim 16

A co-processing system comprising: a first processor having a first instruction set including a first special instruction subset; a second processor having a second instruction set including a second special instruction subset; program memory means for storing program instructions including instructions belonging to said first and second instruction sets, said program memory means having associated address input terminals and data output terminals; first instruction pointer means, associated with said first processor, for storing an address; first instruction pointer control means, associated with said first processor, for incrementing or otherwise modifying the address in said first instruction pointer means in accordance with the operation of said first processor; first instruction register means, associated with said first processor, for storing an instruction belonging to said first instruction set for execution by said first processor; first control passing means, operatively coupled to said first instruction register, for suspending the operation of said first processor and commencing the operation of said second processor when the instruction in said first instruction register belongs to said first special instruction subset; second instruction pointer means, associated with said second processor, for storing an address; second instruction pointer control means, associated with said second processor, for incrementing or otherwise modifying the address in said second instruction pointer means in accordance with the operation of said second processor; second instruction register means, associated with said second processor, for storing an instruction belonging to said second instruction set for execution by said second processor; second control passing means, operatively coupled to said second instruction register, for suspending the operation of said second processor and commencing the operation of said first processor when the instruction in said second instruction register belongs to said second special instruction subset; and means for coordinating the operation of said first and second processors, including address definition means for selectively communicating the content of one of said first and second address register means to said address input terminals, instruction definition means for selectively communicating the data appearing at said data output terminals to one of said first and second instruction register means, processor definition means for selectively enabling one of said first and second processors, and means for conditioning said address definition means, said instruction definition means, and said processor definition means so that at a given time, a given one of said processors operates with its associated instruction pointer means and associated instruction register means to fetch and execute instructions.

Claim 17

A co-processing system comprising: a first processor having a first instruction set including a first special instruction subset; a second processor having a second instruction set including a second special instruction subset; program memory means for storing program instructions including instructions belonging to said first and second instruction sets, said program memory means having associated address input terminals and data output terminals; first instruction pointer means, associated with said first processor, for storing an address; first instruction pointer control means, associated with said first processor, for incrementing or otherwise modifying the address in said first instruction pointer means in accordance with the operation of said first processor; first instruction register means, associated with said first processor, for storing an instruction belonging to said first instruction set for execution by said first processor; first control passing means, operatively coupled to said first instruction register, for suspending the operation of said first processor and commencing the operation of said second processor when the instruction in said first instruction register belongs to said first special instruction subset; second instruction pointer means, associated with said second processor, for storing an address; second instruction pointer control means, associated with said second processor, for incrementing or otherwise modifying the address in said second instruction pointer means in accordance with the operation of said second processor; second instruction register means, associated with said second processor, for storing an instruction belonging to said second instruction set for execution by said second processor; second control passing means, operatively coupled to said second instruction register, for suspending the operation of said second processor and commencing the operation of said first processor when the instruction in said second instruction register belongs to said second special instruction subset; and means for coordinating the operation of said first and second processors, including address definition means for selectively communicating the content of one of said first and second address register means to said address input terminals, instruction definition means for selectively communicating the data appearing at said data output terminals to one of said first and second instruction register means, processor definition means for selectively enabling one of said first and second processors, and means for conditioning said address definition means, said instruction definition means, and said processor definition means so that at a given time, a given one of said processors operates with its associated instruction pointer means and associated instruction register means to fetch and execute instructions.